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-rw-r--r--src/soc/intel/cannonlake/acpi.c19
-rw-r--r--src/soc/intel/cannonlake/chip.c7
-rw-r--r--src/soc/intel/cannonlake/cpu.c19
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c13
-rw-r--r--src/soc/intel/cannonlake/pmc.c3
-rw-r--r--src/soc/intel/cannonlake/smmrelocate.c2
6 files changed, 23 insertions, 40 deletions
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index dce98c4ea6..89770c0586 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -144,8 +144,9 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
ARRAY_SIZE(cstate_set_non_s0ix))];
int *set;
int i;
- struct device *dev = SA_DEV_ROOT;
- config_t *config = dev->chip_info;
+
+ config_t *config = config_of_path(SA_DEVFN_ROOT);
+
int is_s0ix_enable = config->s0ix_enable;
if (is_s0ix_enable) {
@@ -165,18 +166,18 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
void soc_power_states_generation(int core_id, int cores_per_package)
{
- struct device *dev = SA_DEV_ROOT;
- config_t *config = dev->chip_info;
+ config_t *config = config_of_path(SA_DEVFN_ROOT);
+
+ /* Generate P-state tables */
if (config->eist_enable)
- /* Generate P-state tables */
generate_p_state_entries(core_id, cores_per_package);
}
void soc_fill_fadt(acpi_fadt_t *fadt)
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
- const struct device *dev = PCH_DEV_LPC;
- const struct soc_intel_cannonlake_config *config = dev->chip_info;
+ const struct soc_intel_cannonlake_config *config;
+ config = config_of_path(PCH_DEVFN_LPC);
if (!config->PmTimerDisabled) {
fadt->pm_tmr_blk = pmbase + PM1_TMR;
@@ -200,8 +201,8 @@ uint32_t soc_read_sci_irq_select(void)
void acpi_create_gnvs(struct global_nvs_t *gnvs)
{
- const struct device *dev = PCH_DEV_LPC;
- const struct soc_intel_cannonlake_config *config = dev->chip_info;
+ const struct soc_intel_cannonlake_config *config;
+ config = config_of_path(PCH_DEVFN_LPC);
/* Set unknown wake source */
gnvs->pm1i = -1;
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index faddbd5a24..4e0dba5cea 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -170,12 +170,7 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
static void soc_fill_gpio_pm_configuration(void)
{
uint8_t value[TOTAL_GPIO_COMM];
- const struct device *dev;
- dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0);
- if (!dev || !dev->chip_info)
- return;
-
- const config_t *config = dev->chip_info;
+ const config_t *config = config_of_path(SA_DEVFN_ROOT);
if (config->gpio_override_pm)
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 7dae615350..7eb413caa6 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -105,8 +105,8 @@ void set_power_limits(u8 power_limit_1_time)
unsigned int power_unit;
unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
u8 power_limit_1_val;
- struct device *dev = SA_DEV_ROOT;
- config_t *conf = dev->chip_info;
+
+ config_t *conf = config_of_path(SA_DEVFN_ROOT);
if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
power_limit_1_time = 28;
@@ -234,11 +234,10 @@ static void soc_fsp_load(void)
static void configure_isst(void)
{
- struct device *dev = SA_DEV_ROOT;
- config_t *conf = dev->chip_info;
+ config_t *conf = config_of_path(SA_DEVFN_ROOT);
msr_t msr;
- if (conf && conf->speed_shift_enable) {
+ if (conf->speed_shift_enable) {
/*
* Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
* is supported or not. coreboot needs to configure MSR 0x1AA
@@ -260,12 +259,7 @@ static void configure_isst(void)
static void configure_misc(void)
{
- struct device *dev = SA_DEV_ROOT;
- if (!dev) {
- printk(BIOS_ERR, "SA_DEV_ROOT device not found!\n");
- return;
- }
- config_t *conf = dev->chip_info;
+ config_t *conf = config_of_path(SA_DEVFN_ROOT);
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
@@ -367,8 +361,7 @@ static void configure_c_states(void)
static void configure_thermal_target(void)
{
- struct device *dev = SA_DEV_ROOT;
- config_t *conf = dev->chip_info;
+ config_t *conf = config_of_path(SA_DEVFN_ROOT);
msr_t msr;
/* Set TCC activation offset if supported */
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 2367045bdb..cbaa71059f 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -97,13 +97,7 @@ static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params)
static void parse_devicetree(FSP_S_CONFIG *params)
{
- struct device *dev = SA_DEV_ROOT;
- if (!dev) {
- printk(BIOS_ERR, "Could not find root device\n");
- return;
- }
-
- const config_t *config = dev->chip_info;
+ const config_t *config = config_of_path(SA_DEVFN_ROOT);
parse_devicetree_param(config, params);
}
@@ -147,8 +141,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
int i;
FSP_S_CONFIG *params = &supd->FspsConfig;
FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
- struct device *dev = SA_DEV_ROOT;
- config_t *config = dev->chip_info;
+ struct device *dev;
+
+ config_t *config = config_of_path(SA_DEVFN_ROOT);
/* Parse device tree and enable/disable devices */
parse_devicetree(params);
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index 8eb81b0b40..8eadc8db89 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -153,8 +153,7 @@ static void pch_power_options(void)
static void pmc_init(void *unused)
{
- struct device *dev = SA_DEV_ROOT;
- config_t *config = dev->chip_info;
+ config_t *config = config_of_path(SA_DEVFN_ROOT);
rtc_init();
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 47efa18c6c..2576c9c1df 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -256,7 +256,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size)
{
- struct device *dev = SA_DEV_ROOT;
+ struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
printk(BIOS_DEBUG, "Setting up SMI for CPU\n");