diff options
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 25 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/p2sb.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/p2sb.c | 43 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/smihandler.c | 32 |
5 files changed, 54 insertions, 52 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 86f147d0c3..f8f91980bb 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -19,6 +19,7 @@ bootblock-y += i2c.c bootblock-y += memmap.c bootblock-y += spi.c bootblock-y += lpc.c +bootblock-y += p2sb.c bootblock-$(CONFIG_UART_DEBUG) += uart.c romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c @@ -45,6 +46,7 @@ ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += nhlt.c +ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c @@ -56,6 +58,7 @@ ramstage-y += vr_config.c ramstage-y += sd.c smm-y += gpio.c +smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-$(CONFIG_UART_DEBUG) += uart.c diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index dc70a4f6c7..eb67012781 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -18,9 +18,10 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> -#include <intelblocks/rtc.h> #include <intelblocks/pmclib.h> +#include <intelblocks/rtc.h> #include <intelblocks/smbus.h> #include <soc/bootblock.h> #include <soc/iomap.h> @@ -50,25 +51,6 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 -static void enable_p2sbbar(void) -{ - pci_devfn_t dev = PCH_DEV_P2SB; - - /* Enable PCR Base address in PCH */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); - - /* Enable P2SB MSE */ - pci_write_config8(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - /* - * Enable decoding for HPET memory address range. - * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode - * the High Performance Timer memory address range - * selected by bits 1:0 - */ - pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); -} - static void soc_config_pwrmbase(void) { uint32_t reg32; @@ -96,7 +78,8 @@ void bootblock_pch_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); gspi_early_bar_init(); - enable_p2sbbar(); + p2sb_enable_bar(); + p2sb_configure_hpet(); /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/cannonlake/include/soc/p2sb.h b/src/soc/intel/cannonlake/include/soc/p2sb.h index 8b2e437f87..73a50537a3 100644 --- a/src/soc/intel/cannonlake/include/soc/p2sb.h +++ b/src/soc/intel/cannonlake/include/soc/p2sb.h @@ -20,8 +20,5 @@ #define HPTC_ADDR_ENABLE_BIT (1 << 7) #define PCH_P2SB_EPMASK0 0x220 -#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) - -#define PCH_P2SB_E0 0xE0 #endif diff --git a/src/soc/intel/cannonlake/p2sb.c b/src/soc/intel/cannonlake/p2sb.c new file mode 100644 index 0000000000..6a7fac4963 --- /dev/null +++ b/src/soc/intel/cannonlake/p2sb.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <intelblocks/p2sb.h> + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ + uint32_t mask; + + if (count != P2SB_EP_MASK_MAX_REG) { + printk(BIOS_ERR, "Unable to program EPMASK registers\n"); + return; + } + + /* Remove the host accessing right to PSF register range. + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband + * access for PCI Root Bridge. + */ + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); + + ep_mask[P2SB_EP_MASK_5_REG] = mask; + + /* + * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband + * access for Broadcast and Multicast. + */ + mask = (1 << 31) | (1 << 30); + + ep_mask[P2SB_EP_MASK_7_REG] = mask; +} diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 0ecc66df02..5f9e0f82af 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/smihandler.h> #include <soc/p2sb.h> @@ -35,33 +36,8 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void) return &em64t101_smm_ops; } -static void pch_configure_endpoints(pci_devfn_t dev, int epmask_id, - uint32_t mask) -{ - uint32_t reg32; - - reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id)); - pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); -} - -static void disable_sideband_access(pci_devfn_t dev) -{ - u8 reg8; - uint32_t mask; - - /* Remove the host accessing right to PSF register range. */ - /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */ - mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); - pch_configure_endpoints(dev, 5, mask); - - /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ - reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2); - pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1)); -} - static void pch_disable_heci(void) { - pci_devfn_t dev = PCH_DEV_P2SB; struct pcr_sbi_msg msg = { .pid = PID_CSME0, .offset = 0, @@ -77,7 +53,7 @@ static void pch_disable_heci(void) int status; /* unhide p2sb device */ - pci_write_config8(dev, PCH_P2SB_E0 + 1, 0); + p2sb_unhide(); /* Send SBI command to make HECI#1 function disable */ status = pcr_execute_sideband_msg(&msg, &data32, &response); @@ -85,10 +61,10 @@ static void pch_disable_heci(void) printk(BIOS_ERR, "Fail to make CSME function disable\n"); /* Ensure to Lock SBI interface after this command */ - disable_sideband_access(dev); + p2sb_disable_sideband_access(); /* hide p2sb device */ - pci_write_config8(dev, PCH_P2SB_E0 + 1, 1); + p2sb_hide(); } /* |