diff options
Diffstat (limited to 'src/soc/intel/common/block/systemagent/systemagent_early.c')
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent_early.c | 71 |
1 files changed, 0 insertions, 71 deletions
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 8c89c07e26..d6f129d679 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -139,63 +139,12 @@ uintptr_t sa_get_tolud_base(void) return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TOLUD), 1*MiB); } -static uint16_t sa_get_ggc_reg(void) -{ - return pci_read_config16(SA_DEV_ROOT, GGC); -} - -/* - * Internal Graphics Pre-allocated Memory - As per Intel FSP UPD Header - * definition, size of memory preallocatred for internal graphics can be - * configured based on below lists: - * - * 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, - * 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, - * 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, - * 0xFE:60MB - * - * Today all existing SoCs(except Cannonlake) are supported under intel - * common code block design may not need to use any other values than 0x0-0x05 - * for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for - * early SoC samples and validation requirement. This code block to justify - * all differnet possible ranges that FSP may support for a platform. - */ -size_t sa_get_dsm_size(void) -{ - uint32_t prealloc_memory; - uint16_t ggc; - - ggc = sa_get_ggc_reg(); - prealloc_memory = (ggc & G_GMS_MASK) >> G_GMS_OFFSET; - - if (prealloc_memory < 0xF0) - return prealloc_memory * 32*MiB; - else - return (prealloc_memory - 0xEF) * 4*MiB; -} - uintptr_t sa_get_gsm_base(void) { /* All regions concerned for have 1 MiB alignment. */ return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, BGSM), 1*MiB); } -size_t sa_get_gsm_size(void) -{ - uint8_t ggms; - - ggms = (sa_get_ggc_reg() & G_GGMS_MASK) >> G_GGMS_OFFSET; - - /* - * Size of GSM: 0x0: No Preallocated Memory 0x1: 2MB Memory - * 0x2: 4MB Memory 0x3: 8MB Memory - */ - if (ggms) - return 1*MiB << ggms; - else - return 0; -} - uintptr_t sa_get_tseg_base(void) { /* All regions concerned for have 1 MiB alignment. */ @@ -206,23 +155,3 @@ size_t sa_get_tseg_size(void) { return sa_get_gsm_base() - sa_get_tseg_base(); } - -/* - * Get DPR size in case CONFIG_SA_ENABLE_DPR is selected by SoC. - */ -size_t sa_get_dpr_size(void) -{ - uintptr_t dpr_reg; - size_t size = 0; - /* - * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address - * the DPR register reports the TOP of the region, which is the same - * as TSEG base. The region size is reported in MiB in bits 11:4. - */ - dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR); - if (dpr_reg & DPR_EPM) - size = (dpr_reg & DPR_SIZE_MASK) << 16; - - return size; -} |