summaryrefslogtreecommitdiff
path: root/src/soc/intel/common/block
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/cpu/Makefile.inc1
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram.S17
2 files changed, 3 insertions, 15 deletions
diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc
index 5207227b49..a6c4f37cc4 100644
--- a/src/soc/intel/common/block/cpu/Makefile.inc
+++ b/src/soc/intel/common/block/cpu/Makefile.inc
@@ -1,4 +1,5 @@
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_reset.S
bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index d3ee671bef..b1648e8eed 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -28,21 +28,8 @@ bootblock_pre_c_entry:
post_code(0x20)
- /*
- * Use the MTRR default type MSR as a proxy for detecting INIT#.
- * Reset the system if any known bits are set in that MSR. That is
- * an indication of the CPU not being properly reset.
- */
-check_for_clean_reset:
- mov $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
- cmp $0, %eax
- jz no_reset
- /* perform warm reset */
- movw $0xcf9, %dx
- movb $0x06, %al
- outb %al, %dx
+ movl $no_reset, %esp /* return address */
+ jmp check_mtrr /* Check if CPU properly reset */
no_reset:
post_code(0x21)