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Diffstat (limited to 'src/soc/intel/common/stage_cache.c')
-rw-r--r-- | src/soc/intel/common/stage_cache.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/soc/intel/common/stage_cache.c b/src/soc/intel/common/stage_cache.c new file mode 100644 index 0000000000..2dd4e47d9e --- /dev/null +++ b/src/soc/intel/common/stage_cache.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <soc/intel/common/memmap.h> +#include <soc/smm.h> +#include <stage_cache.h> + +void stage_cache_external_region(void **base, size_t *size) +{ + char *smm_base; + size_t smm_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + /* + * The ramstage cache lives in the TSEG region. + * The top of ram is defined to be the TSEG base address. + */ + smm_region((void **)&smm_base, &smm_size); + *size = cache_size; + *base = (void *)(&smm_base[smm_size - cache_size]); +} |