diff options
Diffstat (limited to 'src/soc/intel/common/vbt.c')
| -rw-r--r-- | src/soc/intel/common/vbt.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c new file mode 100644 index 0000000000..302a4a68e5 --- /dev/null +++ b/src/soc/intel/common/vbt.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <fsp_util.h> +#include <lib.h> +#include <soc/intel/common/ramstage.h> +#include <string.h> + +/* Locate VBT and pass it to FSP GOP */ +void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params) +{ + const optionrom_vbt_t *vbt_data; + uint32_t vbt_len; + + /* Check boot mode - for S3 resume path VBT loading is not needed */ + if (s3_resume) { + vbt_data = NULL; + printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n"); + } else { + /* Get VBT data */ + vbt_data = fsp_get_vbt(&vbt_len); + if (vbt_data != NULL) + printk(BIOS_DEBUG, "Passing VBT to GOP\n"); + else + printk(BIOS_DEBUG, "VBT not found!\n"); + } + params->PcdGraphicsConfigPtr = (u32)vbt_data; +} |