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-rw-r--r--src/soc/intel/denverton_ns/include/soc/acpi.h34
-rw-r--r--src/soc/intel/denverton_ns/include/soc/bootblock.h33
-rw-r--r--src/soc/intel/denverton_ns/include/soc/cpu.h45
-rw-r--r--src/soc/intel/denverton_ns/include/soc/fiamux.h27
-rw-r--r--src/soc/intel/denverton_ns/include/soc/gpio.h309
-rw-r--r--src/soc/intel/denverton_ns/include/soc/gpio_defs.h500
-rw-r--r--src/soc/intel/denverton_ns/include/soc/iomap.h40
-rw-r--r--src/soc/intel/denverton_ns/include/soc/lpc.h63
-rw-r--r--src/soc/intel/denverton_ns/include/soc/msr.h114
-rw-r--r--src/soc/intel/denverton_ns/include/soc/nvs.h74
-rw-r--r--src/soc/intel/denverton_ns/include/soc/p2sb.h67
-rw-r--r--src/soc/intel/denverton_ns/include/soc/pattrs.h55
-rw-r--r--src/soc/intel/denverton_ns/include/soc/pci_devs.h204
-rw-r--r--src/soc/intel/denverton_ns/include/soc/pcr.h35
-rw-r--r--src/soc/intel/denverton_ns/include/soc/pm.h59
-rw-r--r--src/soc/intel/denverton_ns/include/soc/pmc.h255
-rw-r--r--src/soc/intel/denverton_ns/include/soc/ramstage.h30
-rw-r--r--src/soc/intel/denverton_ns/include/soc/romstage.h28
-rw-r--r--src/soc/intel/denverton_ns/include/soc/sata.h31
-rw-r--r--src/soc/intel/denverton_ns/include/soc/smbus.h85
-rw-r--r--src/soc/intel/denverton_ns/include/soc/smm.h60
-rw-r--r--src/soc/intel/denverton_ns/include/soc/soc_util.h70
-rw-r--r--src/soc/intel/denverton_ns/include/soc/systemagent.h89
-rw-r--r--src/soc/intel/denverton_ns/include/soc/uart.h27
24 files changed, 2334 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h
new file mode 100644
index 0000000000..dd2be4dd42
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/acpi.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_ACPI_H_
+#define _DENVERTON_NS_ACPI_H_
+
+#include <arch/acpi.h>
+#include <soc/nvs.h>
+
+void acpi_create_intel_hpet(acpi_hpet_t *hpet);
+void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
+void acpi_fill_in_fadt(acpi_fadt_t *fadt);
+unsigned long acpi_madt_irq_overrides(unsigned long current);
+void acpi_init_gnvs(global_nvs_t *gnvs);
+unsigned long southcluster_write_acpi_tables(device_t device,
+ unsigned long current,
+ struct acpi_rsdp *rsdp);
+void southcluster_inject_dsdt(device_t device);
+
+#endif /* _DENVERTON_NS_ACPI_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/bootblock.h b/src/soc/intel/denverton_ns/include/soc/bootblock.h
new file mode 100644
index 0000000000..8e58529770
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/bootblock.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_DENVERTON_NS_BOOTBLOCK_H_
+#define _SOC_DENVERTON_NS_BOOTBLOCK_H_
+
+/* Bootblock pre console init programing */
+//void bootblock_cpu_init(void);
+//void bootblock_pch_early_init(void);
+//void bootblock_systemagent_early_init(void);
+void early_uart_init(void);
+
+/* Bootblock post console init programing */
+//void enable_smbus(void);
+//void i2c_early_init(void);
+//void pch_early_init(void);
+//void report_platform_info(void);
+//void report_memory_config(void);
+//void set_max_freq(void);
+
+#endif
diff --git a/src/soc/intel/denverton_ns/include/soc/cpu.h b/src/soc/intel/denverton_ns/include/soc/cpu.h
new file mode 100644
index 0000000000..7fd2e94af0
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/cpu.h
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _CPU_INTEL_DENVERTON_NS_H
+#define _CPU_INTEL_DENVERTON_NS_H
+
+int get_cpu_count(void);
+
+#ifndef __ASSEMBLER__
+#include <device/device.h>
+
+void denverton_init_cpus(struct device *dev);
+#endif
+
+/* Everything below this line is ignored in the DSDT */
+#ifndef __ACPI__
+
+/* Denverton-NS CPUID */
+#define CPUID_DENVERTON_A0_A1 0x506f0
+#define CPUID_DENVERTON_B0 0x506f1
+
+#define MSR_CORE_THREAD_COUNT 0x35
+#define CORE_BIT_MSK 0x1
+#define MCH_BAR_CORE_EXISTS_MASK 0x7164
+#define MCH_BAR_CORE_DISABLE_MASK 0x7168
+
+/* CPU bus clock is fixed at 100MHz */
+#define CPU_BCLK 100
+
+#endif /* __ACPI__ */
+
+#endif /* _CPU_INTEL_DENVERTON_NS_H */
diff --git a/src/soc/intel/denverton_ns/include/soc/fiamux.h b/src/soc/intel/denverton_ns/include/soc/fiamux.h
new file mode 100644
index 0000000000..e8aaf65f11
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/fiamux.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MAINBOARD_HARCUVAR_FIAMUX_H
+#define _MAINBOARD_HARCUVAR_FIAMUX_H
+
+#include <fsp/util.h>
+
+int get_fiamux_hsio_info(uint16_t num_of_lanes, size_t num_of_entry,
+ BL_HSIO_INFORMATION **config);
+
+BL_FIA_MUX_CONFIG_HOB *get_fiamux_hob_data(void);
+void print_fiamux_config_hob(BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data);
+
+#endif // _MAINBOARD_HARCUVAR_FIAMUX_H
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio.h b/src/soc/intel/denverton_ns/include/soc/gpio.h
new file mode 100644
index 0000000000..964b5e0715
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/gpio.h
@@ -0,0 +1,309 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_GPIO_H_
+#define _DENVERTON_NS_GPIO_H_
+
+#define RShiftU64(Operand, Count) (Operand >> Count)
+#define LShiftU64(Operand, Count) (Operand << Count)
+
+#include <soc/gpio_defs.h>
+
+#ifndef __ACPI__
+#include <stdint.h>
+#include <stddef.h>
+
+//
+// Structure for storing information about registers offset, community,
+// maximal pad number for available groups
+//
+struct GPIO_GROUP_INFO {
+ uint32_t Community;
+ uint32_t PadOwnOffset;
+ uint32_t HostOwnOffset;
+ uint32_t GpiIsOffset;
+ uint32_t GpiIeOffset;
+ uint32_t GpiGpeStsOffset;
+ uint32_t GpiGpeEnOffset;
+ uint32_t SmiStsOffset;
+ uint32_t SmiEnOffset;
+ uint32_t NmiStsOffset;
+ uint32_t NmiEnOffset;
+ uint32_t PadCfgLockOffset;
+ uint32_t PadCfgLockTxOffset;
+ uint32_t PadCfgOffset;
+ uint32_t PadPerGroup;
+};
+
+//
+// If in GPIO_GROUP_INFO structure certain register doesn't exist
+// it will have value equal to NO_REGISTER_FOR_PROPERTY
+//
+#define NO_REGISTER_FOR_PROPERTY (~0u)
+
+//
+// Below defines are based on GPIO_CONFIG structure fields
+//
+#define GPIO_CONF_PAD_MODE_MASK 0xF
+#define GPIO_CONF_PAD_MODE_BIT_POS 0
+#define GPIO_CONF_HOST_OWN_MASK 0x3
+#define GPIO_CONF_HOST_OWN_BIT_POS 0
+#define GPIO_CONF_DIR_MASK 0x7
+#define GPIO_CONF_DIR_BIT_POS 0
+#define GPIO_CONF_INV_MASK 0x18
+#define GPIO_CONF_INV_BIT_POS 3
+#define GPIO_CONF_OUTPUT_MASK 0x3
+#define GPIO_CONF_OUTPUT_BIT_POS 0
+#define GPIO_CONF_INT_ROUTE_MASK 0x1F
+#define GPIO_CONF_INT_ROUTE_BIT_POS 0
+#define GPIO_CONF_INT_TRIG_MASK 0xE0
+#define GPIO_CONF_INT_TRIG_BIT_POS 5
+#define GPIO_CONF_RESET_MASK 0x7
+#define GPIO_CONF_RESET_BIT_POS 0
+#define GPIO_CONF_TERM_MASK 0x1F
+#define GPIO_CONF_TERM_BIT_POS 0
+#define GPIO_CONF_PADTOL_MASK 0x60
+#define GPIO_CONF_PADTOL_BIT_POS 5
+#define GPIO_CONF_LOCK_MASK 0x7
+#define GPIO_CONF_LOCK_BIT_POS 0
+#define GPIO_CONF_RXRAW_MASK 0x3
+#define GPIO_CONF_RXRAW_BIT_POS 0
+
+/**
+GPIO configuration structure used for pin programming.
+Structure contains fields that can be used to configure pad.
+**/
+struct GPIO_CONFIG {
+ /**
+ Pad Mode
+ Pad can be set as GPIO or one of its native functions.
+ When in native mode setting Direction (except Inversion), OutputState,
+ InterruptConfig and Host Software Pad Ownership are unnecessary.
+ Refer to definition of GPIO_PAD_MODE.
+ Refer to EDS for each native mode according to the pad.
+ **/
+ uint32_t PadMode : 4;
+ /**
+ Host Software Pad Ownership
+ Set pad to ACPI mode or GPIO Driver Mode.
+ Refer to definition of GPIO_HOSTSW_OWN.
+ **/
+ uint32_t HostSoftPadOwn : 2;
+ /**
+ GPIO Direction
+ Can choose between In, In with inversion Out, both In and Out, both In
+ with inversion and out or disabling both.
+ Refer to definition of GPIO_DIRECTION for supported settings.
+ **/
+ uint32_t Direction : 5;
+ /**
+ Output State
+ Set Pad output value.
+ Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+ This setting takes place when output is enabled.
+ **/
+ uint32_t OutputState : 2;
+ /**
+ GPIO Interrupt Configuration
+ Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting
+ is applicable only if GPIO is in input mode.
+ If GPIO is set to cause an SCI then also Gpe is enabled for this pad.
+ Refer to definition of GPIO_INT_CONFIG for supported settings.
+ **/
+ uint32_t InterruptConfig : 8;
+ /**
+ GPIO Power Configuration.
+ This setting controls Pad Reset Configuration.
+ Refer to definition of GPIO_RESET_CONFIG for supported settings.
+ **/
+ uint32_t PowerConfig : 4;
+
+ /**
+ GPIO Electrical Configuration
+ This setting controls pads termination and voltage tolerance.
+ Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+ **/
+ uint32_t ElectricalConfig : 7;
+
+ /**
+ GPIO Lock Configuration
+ This setting controls pads lock.
+ Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+ **/
+ uint32_t LockConfig : 3;
+ /**
+ Additional GPIO configuration
+ Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+ **/
+ uint32_t OtherSettings : 2;
+ uint32_t RsvdBits : 27; ///< Reserved bits for future extension
+} __attribute__((packed));
+
+typedef enum { GpioHardwareDefault = 0x0 } GPIO_HARDWARE_DEFAULT;
+
+///
+/// GPIO Pad Mode
+///
+typedef enum {
+ GpioPadModeGpio = 0x1,
+ GpioPadModeNative1 = 0x3,
+ GpioPadModeNative2 = 0x5,
+ GpioPadModeNative3 = 0x7,
+ GpioPadModeNative4 = 0x9
+} GPIO_PAD_MODE;
+
+///
+/// Host Software Pad Ownership modes
+///
+typedef enum {
+ GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
+ GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI
+ GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO
+} GPIO_HOSTSW_OWN;
+
+///
+/// GPIO Direction
+///
+typedef enum {
+ GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
+ GpioDirInOut =
+ (0x1 | (0x1 << 3)), ///< Set pad for both output and input
+ GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and
+ ///input with inversion
+ GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
+ GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
+ GpioDirOut = 0x5, ///< Set pad for output only
+ GpioDirNone = 0x7 ///< Disable both output and input
+} GPIO_DIRECTION;
+
+///
+/// GPIO Output State
+///
+typedef enum {
+ GpioOutDefault = 0x0, ///< Leave output value unmodified
+ GpioOutLow = 0x1, ///< Set output to low
+ GpioOutHigh = 0x3 ///< Set output to high
+} GPIO_OUTPUT_STATE;
+
+///
+/// GPIO interrupt configuration
+/// This setting is applicable only if GPIO is in input mode.
+/// GPIO_INT_CONFIG allows to choose which interrupt is generated
+/// (IOxAPIC/SCI/SMI/NMI)
+/// and how it is triggered (edge or level).
+/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to
+/// GpioIntBothEdgecan
+/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel
+/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad.
+/// Not all GPIO are capable of generating an SMI or NMI interrupt
+///
+
+typedef enum {
+ GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
+ GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
+ GpioIntNmi = 0x3, ///< Enable NMI interrupt only
+ GpioIntSmi = 0x5, ///< Enable SMI interrupt only
+ GpioIntSci = 0x9, ///< Enable SCI interrupt only
+ GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
+ GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
+ GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of
+ ///edge depends on input inversion)
+ GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
+ GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
+} GPIO_INT_CONFIG;
+
+///
+/// GPIO Power Configuration
+/// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified
+/// Pad Register fields).
+///
+typedef enum {
+ GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified
+ GpioResetPwrGood = 0x1, ///< Powergood reset
+ GpioResetDeep = 0x3, ///< Deep GPIO Reset
+ GpioResetNormal = 0x5, ///< GPIO Reset
+ GpioResetResume = 0x7 ///< Resume Reset (applicable only for GPD group)
+} GPIO_RESET_CONFIG;
+
+///
+/// GPIO Electrical Configuration
+/// Set GPIO termination and Pad Tolerance (applicable only for some pads)
+/// Field from GpioTermDefault to GpioTermNative can be OR'ed with
+/// GpioTolerance1v8.
+///
+typedef enum {
+ GpioTermDefault = 0x0, ///< Leave termination setting unmodified
+ GpioTermNone = 0x1, ///< none
+ GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
+ GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
+ GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
+ GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
+ GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
+ GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
+ GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
+ GpioTermNative = 0x1F, ///< Native function controls pads termination
+ GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance
+ GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance
+} GPIO_ELECTRICAL_CONFIG;
+
+///
+/// GPIO LockConfiguration
+/// Set GPIO configuration lock and output state lock
+/// GpioLockPadConfig and GpioLockOutputState can be OR'ed
+///
+typedef enum {
+ GpioLockDefault = 0x0, ///< Leave lock setting unmodified
+ GpioPadConfigLock = 0x3, ///< Lock Pad Configuration
+ GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value
+} GPIO_LOCK_CONFIG;
+
+///
+/// Other GPIO Configuration
+/// GPIO_OTHER_CONFIG is used for less often settings and for future extensions
+/// Supported settings:
+/// - RX raw override to '1' - allows to override input value to '1'
+/// This setting is applicable only if in input mode (both in GPIO and
+/// native usage).
+/// The override takes place at the internal pad state directly from buffer
+/// and before the RXINV.
+///
+typedef enum {
+ GpioRxRaw1Default = 0x0, ///< Use default input override value
+ GpioRxRaw1Dis = 0x1, ///< Don't override input
+ GpioRxRaw1En = 0x3 ///< Override input to '1'
+} GPIO_OTHER_CONFIG;
+
+//
+// Possible values of Pad Ownership
+//
+typedef enum {
+ GpioPadOwnHost = 0x0,
+ GpioPadOwnCsme = 0x1,
+ GpioPadOwnIsh = 0x2,
+} GPIO_PAD_OWN;
+
+typedef uint32_t GPIO_PAD;
+
+struct pad_config {
+ GPIO_PAD GpioPad;
+ struct GPIO_CONFIG GpioConfig;
+};
+
+/* Configure GPIOs with mainboard provided settings */
+void gpio_configure_pads(const struct pad_config *gpio, size_t num);
+
+#endif /* __ACPI__ */
+#endif /* _DENVERTON_NS_GPIO_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h
new file mode 100644
index 0000000000..9b63a0837c
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h
@@ -0,0 +1,500 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (C) 2015-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_GPIO_DEFS_H_
+#define _DENVERTON_NS_GPIO_DEFS_H_
+
+#include <soc/pcr.h>
+
+/*
+* There are 3 GPIO groups. North Community, South Community DFX/Group0/Group1.
+* The GPIO groups are accessed through register blocks called communities.
+*/
+
+#define V_PCH_GPIO_NC_PAD_MAX 41
+#define V_PCH_GPIO_SC_DFX_PAD_MAX 18
+#define V_PCH_GPIO_SC0_PAD_MAX 53
+#define V_PCH_GPIO_SC1_PAD_MAX 42
+#define V_PCH_GPIO_GROUP_MAX 4
+
+//
+// GPIO Community 0 Private Configuration Registers
+//
+
+//
+// Power Group NORTH_ALL
+//
+#define R_PCH_PCR_GPIO_NC_PAD_OWN 0x20
+#define R_PCH_PCR_GPIO_NC_GPI_VWM_EN 0x70
+#define R_PCH_PCR_GPIO_NC_PADCFGLOCK 0x90
+#define R_PCH_PCR_GPIO_NC_PADCFGLOCKTX 0x94
+#define R_PCH_PCR_GPIO_NC1_PADCFGLOCK_1 0x98
+#define R_PCH_PCR_GPIO_NC1_PADCFGLOCKTX_1 0x9C
+#define R_PCH_PCR_GPIO_NC_HOSTSW_OWN 0xC0
+#define R_PCH_PCR_GPIO_NC_GPI_IS 0x0100
+#define R_PCH_PCR_GPIO_NC_GPI_IE 0x0120
+#define R_PCH_PCR_GPIO_NC_GPI_GPE_STS 0x0140
+#define R_PCH_PCR_GPIO_NC_GPI_GPE_EN 0x0160
+#define R_PCH_PCR_GPIO_NC_SMI_STS 0x0180
+#define R_PCH_PCR_GPIO_NC_SMI_EN 0x01A0
+#define R_PCH_PCR_GPIO_NC_NMI_STS 0x01C0
+#define R_PCH_PCR_GPIO_NC_NMI_EN 0x01E0
+#define R_PCH_PCR_GPIO_NC_PADCFG_OFFSET 0x400
+
+//
+// GPIO Community 1 Private Configuration Registers
+//
+
+//
+// Power Group SOUTH_DFX
+//
+#define R_PCH_PCR_GPIO_SC_DFX_PAD_OWN 0x20
+#define R_PCH_PCR_GPIO_SC_DFX_GPI_VWM_EN 0x70
+#define R_PCH_PCR_GPIO_SC_DFX_PADCFGLOCK 0x90
+#define R_PCH_PCR_GPIO_SC_DFX_PADCFGLOCKTX 0x94
+#define R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN 0xC0
+#define R_PCH_PCR_GPIO_SC_DFX_GPI_IS 0x0100
+#define R_PCH_PCR_GPIO_SC_DFX_GPI_IE 0x0120
+#define R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS 0x0140
+#define R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN 0x0160
+#define R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET 0x400
+//
+// Power Group SOUTH_GROUP0
+//
+#define R_PCH_PCR_GPIO_SC0_PAD_OWN 0x2C
+#define R_PCH_PCR_GPIO_SC0_GPI_VWM_EN 0x74
+#define R_PCH_PCR_GPIO_SC0_PADCFGLOCK 0x98
+#define R_PCH_PCR_GPIO_SC0_PADCFGLOCKTX 0x9C
+#define R_PCH_PCR_GPIO_SC0_HOSTSW_OWN 0xC4
+#define R_PCH_PCR_GPIO_SC0_GPI_IS 0x0104
+#define R_PCH_PCR_GPIO_SC0_GPI_IE 0x0124
+#define R_PCH_PCR_GPIO_SC0_GPI_GPE_STS 0x0144
+#define R_PCH_PCR_GPIO_SC0_GPI_GPE_EN 0x0164
+#define R_PCH_PCR_GPIO_SC0_SMI_STS 0x0184
+#define R_PCH_PCR_GPIO_SC0_SMI_EN 0x01A4
+#define R_PCH_PCR_GPIO_SC0_NMI_STS 0x01C4
+#define R_PCH_PCR_GPIO_SC0_NMI_EN 0x01E4
+#define R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET 0x490
+//
+// Power Group SOUTH_GROUP1
+//
+#define R_PCH_PCR_GPIO_SC1_PAD_OWN 0x48
+#define R_PCH_PCR_GPIO_SC1_GPI_VWM_EN 0x7C
+#define R_PCH_PCR_GPIO_SC1_PADCFGLOCK 0xA8
+#define R_PCH_PCR_GPIO_SC1_PADCFGLOCKTX 0xAC
+#define R_PCH_PCR_GPIO_SC1_HOSTSW_OWN 0xCC
+#define R_PCH_PCR_GPIO_SC1_GPI_IS 0x010C
+#define R_PCH_PCR_GPIO_SC1_GPI_IE 0x012C
+#define R_PCH_PCR_GPIO_SC1_GPI_GPE_STS 0x014C
+#define R_PCH_PCR_GPIO_SC1_GPI_GPE_EN 0x016C
+#define R_PCH_PCR_GPIO_SC1_SMI_STS 0x018C
+#define R_PCH_PCR_GPIO_SC1_SMI_EN 0x01AC
+#define R_PCH_PCR_GPIO_SC1_NMI_STS 0x01CC
+#define R_PCH_PCR_GPIO_SC1_NMI_EN 0x01EC
+#define R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET 0x638
+
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_NORTH_ALL_0 0x90
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_NORTH_ALL_0 0x94
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_NORTH_ALL_1 0x98
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_NORTH_ALL_1 0x9C
+
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_DFX_0 0x90
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_DFX_0 0x94
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP0_0 0x98
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP0_0 0x9C
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP0_1 0xA0
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP0_1 0xA4
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP1_0 0xA8
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP1_0 0xAC
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCK_SOUTH_GROUP1_1 0xB0
+#define R_PCH_PCR_GPIO_GPP_PADCFGLOCKTX_SOUTH_GROUP1_1 0xB4
+
+//
+// Pad Configuration Register DW0
+//
+
+// Pad Reset Config
+#define B_PCH_GPIO_RST_CONF ((1 << 31) | (1 << 30))
+#define N_PCH_GPIO_RST_CONF 30
+#define V_PCH_GPIO_RST_CONF_POW_GOOD 0x00
+#define V_PCH_GPIO_RST_CONF_DEEP_RST 0x01
+#define V_PCH_GPIO_RST_CONF_GPIO_RST 0x02
+#define V_PCH_GPIO_RST_CONF_RESUME_RST 0x03 // Only for GPD Group
+
+// RX Pad State Select
+#define B_PCH_GPIO_RX_PAD_STATE (1 << 29)
+#define N_PCH_GPIO_RX_PAD_STATE 29
+#define V_PCH_GPIO_RX_PAD_STATE_RAW 0x00
+#define V_PCH_GPIO_RX_PAD_STATE_INT 0x01
+
+// RX Raw Overrride to 1
+#define B_PCH_GPIO_RX_RAW1 (1 << 28)
+#define N_PCH_GPIO_RX_RAW1 28
+#define V_PCH_GPIO_RX_RAW1_DIS 0x00
+#define V_PCH_GPIO_RX_RAW1_EN 0x01
+
+// RX Level/Edge Configuration
+#define B_PCH_GPIO_RX_LVL_EDG ((1 << 26) | (1 << 25))
+#define N_PCH_GPIO_RX_LVL_EDG 25
+#define V_PCH_GPIO_RX_LVL_EDG_LVL 0x00
+#define V_PCH_GPIO_RX_LVL_EDG_EDG 0x01
+#define V_PCH_GPIO_RX_LVL_EDG_0 0x02
+#define V_PCH_GPIO_RX_LVL_EDG_RIS_FAL 0x03
+
+// RX Level/Edge Configuration
+#define B_PCH_GPIO_PRE_GFRX_SEL (1 << 24)
+#define N_PCH_GPIO_PRE_GFRX_SEL 24
+#define V_PCH_GPIO_PRE_GFRX_SEL_DIS 0x00
+#define V_PCH_GPIO_PRE_GFRX_SEL_EN 0x01
+
+// RX Invert
+#define B_PCH_GPIO_RXINV (1 << 23)
+#define N_PCH_GPIO_RXINV 23
+#define V_PCH_GPIO_RXINV_NO 0x00
+#define V_PCH_GPIO_RXINV_YES 0x01
+
+// RXTXENCFG
+#define B_PCH_GPIO_RXTXENCFG ((1 << 22) | (1 << 21))
+#define N_PCH_GPIO_RXTXENCFG 21
+#define V_PCH_GPIO_RXTXENCFG_DEF_FUN 0x00
+#define V_PCH_GPIO_RXTXENCFG_TX_EN_L 0x01
+#define V_PCH_GPIO_RXTXENCFG_TX_EN_H 0x02
+#define V_PCH_GPIO_RXTXENCFG_TXRXEN 0x03
+
+// GPIO Input Route IOxAPIC
+#define B_PCH_GPIO_RX_APIC_ROUTE (1 << 20)
+#define N_PCH_GPIO_RX_APIC_ROUTE 20
+#define V_PCH_GPIO_RX_APIC_ROUTE_DIS 0x00
+#define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01
+
+// GPIO Input Route SCI
+#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 10)
+#define N_PCH_GPIO_RX_SCI_ROUTE 19
+#define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00
+#define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01
+
+// GPIO Input Route SMI
+#define B_PCH_GPIO_RX_SMI_ROUTE (1 << 18)
+#define N_PCH_GPIO_RX_SMI_ROUTE 18
+#define V_PCH_GPIO_RX_SMI_ROUTE_DIS 0x00
+#define V_PCH_GPIO_RX_SMI_ROUTE_EN 0x01
+
+// GPIO Input Route NMI
+#define B_PCH_GPIO_RX_NMI_ROUTE (1 << 17)
+#define N_PCH_GPIO_RX_NMI_ROUTE 17
+#define V_PCH_GPIO_RX_NMI_ROUTE_DIS 0x00
+#define V_PCH_GPIO_RX_NMI_ROUTE_EN 0x01
+
+// GPIO Pad Mode
+#define B_PCH_GPIO_PAD_MODE ((1 << 12) | (1 << 11) | (1 << 10))
+#define N_PCH_GPIO_PAD_MODE 10
+#define V_PCH_GPIO_PAD_MODE_GPIO 0
+#define V_PCH_GPIO_PAD_MODE_NAT_1 1
+#define V_PCH_GPIO_PAD_MODE_NAT_2 2
+#define V_PCH_GPIO_PAD_MODE_NAT_3 3
+#define V_PCH_GPIO_PAD_MODE_NAT_4 4
+#define V_PCH_GPIO_PAD_MODE_NAT_5 5
+#define V_PCH_GPIO_PAD_MODE_NAT_6 6
+#define V_PCH_GPIO_PAD_MODE_NAT_7 7
+
+// GPIO RX Disable
+#define B_PCH_GPIO_RXDIS (1 << 9)
+#define N_PCH_GPIO_RXDIS 9
+#define V_PCH_GPIO_RXDIS_EN 0x00
+#define V_PCH_GPIO_RXDIS_DIS 0x01
+
+// GPIO TX Disable
+#define B_PCH_GPIO_TXDIS (1 << 8)
+#define N_PCH_GPIO_TXDIS 8
+#define V_PCH_GPIO_TXDIS_EN 0x00
+#define V_PCH_GPIO_TXDIS_DIS 0x01
+
+// GPIO RX State
+#define B_PCH_GPIO_RX_STATE (1 << 1)
+#define N_PCH_GPIO_RX_STATE 1
+#define V_PCH_GPIO_RX_STATE_LOW 0x00
+#define V_PCH_GPIO_RX_STATE_HIGH 0x01
+
+// GPIO TX State
+#define B_PCH_GPIO_TX_STATE (1 << 0)
+#define N_PCH_GPIO_TX_STATE 0
+#define V_PCH_GPIO_TX_STATE_LOW 0x00
+#define V_PCH_GPIO_TX_STATE_HIGH 0x01
+
+//
+// Pad Configuration Register DW1
+//
+
+// Padtol
+#define B_PCH_GPIO_PADTOL (1 << 25)
+#define N_PCH_GPIO_PADTOL 25
+#define V_PCH_GPIO_PADTOL_NONE 0x00
+#define V_PCH_GPIO_PADTOL_CLEAR 0x00
+#define V_PCH_GPIO_PADTOL_SET 0x01
+
+// Termination
+#define B_PCH_GPIO_TERM ((1 << 13) | (1 << 12) | (1 << 11) | (1 << 10))
+#define N_PCH_GPIO_TERM 10
+#define V_PCH_GPIO_TERM_WPD_NONE 0x00
+#define V_PCH_GPIO_TERM_WPD_5K 0x02
+#define V_PCH_GPIO_TERM_WPD_20K 0x04
+#define V_PCH_GPIO_TERM_WPU_NONE 0x08
+#define V_PCH_GPIO_TERM_WPU_1K 0x09
+#define V_PCH_GPIO_TERM_WPU_2K 0x0B
+#define V_PCH_GPIO_TERM_WPU_5K 0x0A
+#define V_PCH_GPIO_TERM_WPU_20K 0x0C
+#define V_PCH_GPIO_TERM_WPU_1K_2K 0x0D
+#define V_PCH_GPIO_TERM_NATIVE 0x0F
+
+#define PID_NorthCommunity PID_GPIOCOM0
+#define PID_SouthCommunity PID_GPIOCOM1
+
+// GPIO_MISC0
+// HSUART0: 101, 102, 13, 98
+// HSUART1: 96, 97,95 94
+
+#define GPIO_SMB3_CLTT_DATA 12
+#define R_PAD_CFG_DW0_SMB3_CLTT_DATA 0x490
+#define PID_SMB3_CLTT_DATA PID_SouthCommunity
+
+#define GPIO_SMB3_CLTT_CLK 13
+#define R_PAD_CFG_DW0_SMB3_CLTT_CLK 0x498
+#define PID_SMB3_CLTT_CLK PID_SouthCommunity
+
+#define GPIO_PCIE_CLKREQ5_N 98
+#define R_PAD_CFG_DW0_PCIE_CLKREQ5_N 0x4A0
+#define PID_PCIE_CLKREQ5_N PID_SouthCommunity
+
+#define GPIO_PCIE_CLKREQ6_N 99
+#define R_PAD_CFG_DW0_PCIE_CLKREQ6_N 0x4a8
+#define PID_PCIE_CLKREQ6_N PID_SouthCommunity
+
+#define GPIO_PCIE_CLKREQ7_N 100
+#define R_PAD_CFG_DW0_PCIE_CLKREQ7_N 0x4b0
+#define PID_PCIE_CLKREQ7_N PID_SouthCommunity
+
+#define GPIO_UART0_RXD 101
+#define R_PAD_CFG_DW0_UART0_RXD 0x4b8
+#define PID_UART0_RXD PID_SouthCommunity
+
+#define GPIO_UART0_TXD 102
+#define R_PAD_CFG_DW0_UART0_TXD 0x4c0
+#define PID_UART0_TXD PID_SouthCommunity
+
+#define GPIO_UART1_RXD 96
+#define R_PAD_CFG_DW0_UART1_RXD 0x5b8
+#define PID_UART1_RXD PID_SouthCommunity
+
+#define GPIO_UART1_TXD 97
+#define R_PAD_CFG_DW0_UART1_TXD 0x5c0
+#define PID_UART1_TXD PID_SouthCommunity
+
+#define GPIO_SATA1_SDOUT 95
+#define R_PAD_CFG_DW0_SATA1_SDOUT 0x5b0
+#define PID_SATA1_SDOUT PID_SouthCommunity
+
+#define GPIO_SATA0_SDOUT 94
+#define R_PAD_CFG_DW0_SATA0_SDOUT 0x5a8
+#define PID_SATA0_SDOUT PID_SouthCommunity
+
+///
+/// Denverton GPIO Groups
+///
+
+#define GPIO_DNV_GROUP_NC 0x0100
+#define GPIO_DNV_GROUP_SC_DFX 0x0101
+#define GPIO_DNV_GROUP_SC0 0x0102
+#define GPIO_DNV_GROUP_SC1 0x0103
+#define GPIO_DNV_GROUP_MIN GPIO_DNV_GROUP_NC
+#define GPIO_DNV_GROUP_MAX GPIO_DNV_GROUP_SC1
+#define NORTH_ALL_GBE0_SDP0 0x01000000
+#define NORTH_ALL_GBE1_SDP0 0x01000001
+#define NORTH_ALL_GBE0_SDP1 0x01000002
+#define NORTH_ALL_GBE1_SDP1 0x01000003
+#define NORTH_ALL_GBE0_SDP2 0x01000004
+#define NORTH_ALL_GBE1_SDP2 0x01000005
+#define NORTH_ALL_GBE0_SDP3 0x01000006
+#define NORTH_ALL_GBE1_SDP3 0x01000007
+#define NORTH_ALL_GBE2_LED0 0x01000008
+#define NORTH_ALL_GBE2_LED1 0x01000009
+#define NORTH_ALL_GBE0_I2C_CLK 0x0100000A
+#define NORTH_ALL_GBE0_I2C_DATA 0x0100000B
+#define NORTH_ALL_GBE1_I2C_CLK 0x0100000C
+#define NORTH_ALL_GBE1_I2C_DATA 0x0100000D
+#define NORTH_ALL_NCSI_RXD0 0x0100000E
+#define NORTH_ALL_NCSI_CLK_IN 0x0100000F
+#define NORTH_ALL_NCSI_RXD1 0x01000010
+#define NORTH_ALL_NCSI_CRS_DV 0x01000011
+#define NORTH_ALL_NCSI_ARB_IN 0x01000012
+#define NORTH_ALL_NCSI_TX_EN 0x01000013
+#define NORTH_ALL_NCSI_TXD0 0x01000014
+#define NORTH_ALL_NCSI_TXD1 0x01000015
+#define NORTH_ALL_NCSI_ARB_OUT 0x01000016
+#define NORTH_ALL_GBE0_LED0 0x01000017
+#define NORTH_ALL_GBE0_LED1 0x01000018
+#define NORTH_ALL_GBE1_LED0 0x01000019
+#define NORTH_ALL_GBE1_LED1 0x0100001A
+#define NORTH_ALL_GPIO_0 0x0100001B
+#define NORTH_ALL_PCIE_CLKREQ0_N 0x0100001C
+#define NORTH_ALL_PCIE_CLKREQ1_N 0x0100001D
+#define NORTH_ALL_PCIE_CLKREQ2_N 0x0100001E
+#define NORTH_ALL_PCIE_CLKREQ3_N 0x0100001F
+#define NORTH_ALL_PCIE_CLKREQ4_N 0x01000020
+#define NORTH_ALL_GPIO_1 0x01000021
+#define NORTH_ALL_GPIO_2 0x01000022
+#define NORTH_ALL_SVID_ALERT_N 0x01000023
+#define NORTH_ALL_SVID_DATA 0x01000024
+#define NORTH_ALL_SVID_CLK 0x01000025
+#define NORTH_ALL_THERMTRIP_N 0x01000026
+#define NORTH_ALL_PROCHOT_N 0x01000027
+#define NORTH_ALL_MEMHOT_N 0x01000028
+#define SOUTH_DFX_DFX_PORT_CLK0 0x01010000
+#define SOUTH_DFX_DFX_PORT_CLK1 0x01010001
+#define SOUTH_DFX_DFX_PORT0 0x01010002
+#define SOUTH_DFX_DFX_PORT1 0x01010003
+#define SOUTH_DFX_DFX_PORT2 0x01010004
+#define SOUTH_DFX_DFX_PORT3 0x01010005
+#define SOUTH_DFX_DFX_PORT4 0x01010006
+#define SOUTH_DFX_DFX_PORT5 0x01010007
+#define SOUTH_DFX_DFX_PORT6 0x01010008
+#define SOUTH_DFX_DFX_PORT7 0x01010009
+#define SOUTH_DFX_DFX_PORT8 0x0101000A
+#define SOUTH_DFX_DFX_PORT9 0x0101000B
+#define SOUTH_DFX_DFX_PORT10 0x0101000C
+#define SOUTH_DFX_DFX_PORT11 0x0101000D
+#define SOUTH_DFX_DFX_PORT12 0x0101000E
+#define SOUTH_DFX_DFX_PORT13 0x0101000F
+#define SOUTH_DFX_DFX_PORT14 0x01010010
+#define SOUTH_DFX_DFX_PORT15 0x01010011
+#define SOUTH_GROUP0_SMB3_CLTT_DATA 0x01020000
+#define SOUTH_GROUP0_SMB3_CLTT_CLK 0x01020001
+#define SOUTH_GROUP0_GPIO_12 0x01020000
+#define SOUTH_GROUP0_SMB5_GBE_ALRT_N 0x01020001
+#define SOUTH_GROUP0_PCIE_CLKREQ5_N 0x01020002
+#define SOUTH_GROUP0_PCIE_CLKREQ6_N 0x01020003
+#define SOUTH_GROUP0_PCIE_CLKREQ7_N 0x01020004
+#define SOUTH_GROUP0_UART0_RXD 0x01020005
+#define SOUTH_GROUP0_UART0_TXD 0x01020006
+#define SOUTH_GROUP0_SMB5_GBE_CLK 0x01020007
+#define SOUTH_GROUP0_SMB5_GBE_DATA 0x01020008
+#define SOUTH_GROUP0_ERROR2_N 0x01020009
+#define SOUTH_GROUP0_ERROR1_N 0x0102000A
+#define SOUTH_GROUP0_ERROR0_N 0x0102000B
+#define SOUTH_GROUP0_IERR_N 0x0102000C
+#define SOUTH_GROUP0_MCERR_N 0x0102000D
+#define SOUTH_GROUP0_SMB0_LEG_CLK 0x0102000E
+#define SOUTH_GROUP0_SMB0_LEG_DATA 0x0102000F
+#define SOUTH_GROUP0_SMB0_LEG_ALRT_N 0x01020010
+#define SOUTH_GROUP0_SMB1_HOST_DATA 0x01020011
+#define SOUTH_GROUP0_SMB1_HOST_CLK 0x01020012
+#define SOUTH_GROUP0_SMB2_PECI_DATA 0x01020013
+#define SOUTH_GROUP0_SMB2_PECI_CLK 0x01020014
+#define SOUTH_GROUP0_SMB4_CSME0_DATA 0x01020015
+#define SOUTH_GROUP0_SMB4_CSME0_CLK 0x01020016
+#define SOUTH_GROUP0_SMB4_CSME0_ALRT_N 0x01020017
+#define SOUTH_GROUP0_USB_OC0_N 0x01020018
+#define SOUTH_GROUP0_FLEX_CLK_SE0 0x01020019
+#define SOUTH_GROUP0_FLEX_CLK_SE1 0x0102001A
+#define SOUTH_GROUP0_GPIO_4 0x0102001B
+#define SOUTH_GROUP0_GPIO_5 0x0102001C
+#define SOUTH_GROUP0_GPIO_6 0x0102001D
+#define SOUTH_GROUP0_GPIO_7 0x0102001E
+#define SOUTH_GROUP0_SATA0_LED_N 0x0102001F
+#define SOUTH_GROUP0_SATA1_LED_N 0x01020020
+#define SOUTH_GROUP0_SATA_PDETECT0 0x01020021
+#define SOUTH_GROUP0_SATA_PDETECT1 0x01020022
+#define SOUTH_GROUP0_SATA0_SDOUT 0x01020023
+#define SOUTH_GROUP0_SATA1_SDOUT 0x01020024
+#define SOUTH_GROUP0_UART1_RXD 0x01020025
+#define SOUTH_GROUP0_UART1_TXD 0x01020026
+#define SOUTH_GROUP0_GPIO_8 0x01020027
+#define SOUTH_GROUP0_GPIO_9 0x01020028
+#define SOUTH_GROUP0_TCK 0x01020029
+#define SOUTH_GROUP0_TRST_N 0x0102002A
+#define SOUTH_GROUP0_TMS 0x0102002B
+#define SOUTH_GROUP0_TDI 0x0102002C
+#define SOUTH_GROUP0_TDO 0x0102002D
+#define SOUTH_GROUP0_CX_PRDY_N 0x0102002E
+#define SOUTH_GROUP0_CX_PREQ_N 0x0102002F
+#define SOUTH_GROUP0_CTBTRIGINOUT 0x01020030
+#define SOUTH_GROUP0_CTBTRIGOUT 0x01020031
+#define SOUTH_GROUP0_DFX_SPARE2 0x01020032
+#define SOUTH_GROUP0_DFX_SPARE3 0x01020033
+#define SOUTH_GROUP0_DFX_SPARE4 0x01020034
+#define SOUTH_GROUP1_SUSPWRDNACK 0x01030000
+#define SOUTH_GROUP1_PMU_SUSCLK 0x01030001
+#define SOUTH_GROUP1_ADR_TRIGGER 0x01030002
+#define SOUTH_GROUP1_PMU_AC_PRESENT 0x01030002
+#define SOUTH_GROUP1_PMU_SLP_S45_N 0x01030003
+#define SOUTH_GROUP1_PMU_SLP_S3_N 0x01030004
+#define SOUTH_GROUP1_PMU_WAKE_N 0x01030005
+#define SOUTH_GROUP1_PMU_PWRBTN_N 0x01030006
+#define SOUTH_GROUP1_PMU_RESETBUTTON_N 0x01030007
+#define SOUTH_GROUP1_PMU_PLTRST_N 0x01030008
+#define SOUTH_GROUP1_SUS_STAT_N 0x01030009
+#define SOUTH_GROUP1_SLP_S0IX_N 0x0103000A
+#define SOUTH_GROUP1_SPI_CS0_N 0x0103000B
+#define SOUTH_GROUP1_SPI_CS1_N 0x0103000C
+#define SOUTH_GROUP1_SPI_MOSI_IO0 0x0103000D
+#define SOUTH_GROUP1_SPI_MISO_IO1 0x0103000E
+#define SOUTH_GROUP1_SPI_IO2 0x0103000F
+#define SOUTH_GROUP1_SPI_IO3 0x01030010
+#define SOUTH_GROUP1_SPI_CLK 0x01030011
+#define SOUTH_GROUP1_SPI_CLK_LOOPBK 0x01030012
+#define SOUTH_GROUP1_ESPI_IO0 0x01030013
+#define SOUTH_GROUP1_ESPI_IO1 0x01030014
+#define SOUTH_GROUP1_ESPI_IO2 0x01030015
+#define SOUTH_GROUP1_ESPI_IO3 0x01030016
+#define SOUTH_GROUP1_ESPI_CS0_N 0x01030017
+#define SOUTH_GROUP1_ESPI_CLK 0x01030018
+#define SOUTH_GROUP1_ESPI_RST_N 0x01030019
+#define SOUTH_GROUP1_ESPI_ALRT0_N 0x0103001A
+#define SOUTH_GROUP1_GPIO_10 0x0103001B
+#define SOUTH_GROUP1_GPIO_11 0x0103001C
+#define SOUTH_GROUP1_ESPI_CLK_LOOPBK 0x0103001D
+#define SOUTH_GROUP1_EMMC_CMD 0x0103001E
+#define SOUTH_GROUP1_EMMC_STROBE 0x0103001F
+#define SOUTH_GROUP1_EMMC_CLK 0x01030020
+#define SOUTH_GROUP1_EMMC_D0 0x01030021
+#define SOUTH_GROUP1_EMMC_D1 0x01030022
+#define SOUTH_GROUP1_EMMC_D2 0x01030023
+#define SOUTH_GROUP1_EMMC_D3 0x01030024
+#define SOUTH_GROUP1_EMMC_D4 0x01030025
+#define SOUTH_GROUP1_EMMC_D5 0x01030026
+#define SOUTH_GROUP1_EMMC_D6 0x01030027
+#define SOUTH_GROUP1_EMMC_D7 0x01030028
+#define SOUTH_GROUP1_GPIO_3 0x01030029
+
+// BIT15-0 - pad number
+// BIT31-16 - group info
+// BIT23- 16 - group index
+// BIT31- 24 - chipset ID (default to 0x01)
+#define PAD_INFO_MASK 0x0000FFFF
+#define GROUP_INFO_POSITION 16
+#define GROUP_INFO_MASK 0xFFFF0000
+#define GROUP_INDEX_MASK 0x00FF0000
+#define UNIQUE_ID_MASK 0xFF000000
+#define UNIQUE_ID_POSITION 24
+
+#define GPIO_PAD_DEF(Group, Pad) (uint32_t)((Group << 16) + Pad)
+#define GPIO_GET_GROUP_INDEX(Group) (Group & 0xFF)
+#define GPIO_GET_GROUP_FROM_PAD(Pad) (Pad >> 16)
+#define GPIO_GET_GROUP_INDEX_FROM_PAD(Pad) GPIO_GET_GROUP_INDEX((Pad >> 16))
+#define GPIO_GET_PAD_NUMBER(Pad) (Pad & 0xFFFF)
+#define GPIO_GET_CHIPSET_ID(Pad) (Pad >> 24)
+
+#endif /* _DENVERTON_NS_GPIO_DEFS_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h
new file mode 100644
index 0000000000..29b231f10d
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/iomap.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_IOMAP_H_
+#define _DENVERTON_NS_IOMAP_H_
+
+/*
+ * Memory Mapped IO bases.
+ */
+
+/* Northbridge BARs */
+#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
+#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
+
+/* Southbridge internal device IO BARs (Set to match FSP settings) */
+#define DEFAULT_PMBASE 0x1800
+#define DEFAULT_ACPI_BASE DEFAULT_PMBASE
+#define DEFAULT_TCO_BASE 0x400
+
+/* Southbridge internal device MEM BARs (Set to match FSP settings) */
+#define DEFAULT_PCR_BASE 0xfd000000
+#define DEFAULT_PWRM_BASE 0xfe000000
+#define DEFAULT_HPET_ADDR CONFIG_HPET_ADDRESS
+#define DEFAULT_SPI_BASE 0xfed01000
+
+#endif /* _DENVERTON_NS_IOMAP_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/lpc.h b/src/soc/intel/denverton_ns/include/soc/lpc.h
new file mode 100644
index 0000000000..b1b4462c14
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/lpc.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_LPC_H_
+#define _DENVERTON_NS_LPC_H_
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEV PCI_DEV(0, LPC_DEV, LPC_FUNC)
+
+#define SERIRQ_CNTL 0x64
+#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define FDD_LPC_SHIFT 12 /* LPC_IO_DEC[12] */
+#define FDD_DEC_MASK 1
+#define FDD_DEC_3F8 0 /* 3F0h - 3F5Fh, 3F7h (Primary) */
+#define FDD_DEC_2F8 1 /* 370h - 375h, 377h (Secondary) */
+#define LPT_LPC_SHIFT 8 /* LPC_IO_DEC[9:8] */
+#define LPT_DEC_MASK 3
+#define LPT_DEC_378 0 /* 378h - 37Fh and 778h - 77Fh */
+#define LPT_DEC_278 1 /* 278h - 27Fh and 678h - 67Fh */
+#define LPT_DEC_3BC 2 /* 3BCh - 3BEh and 7BCh - 7BEh */
+#define COMB_LPC_SHIFT 4 /* LPC_IO_DEC[6:4] */
+#define COMA_LPC_SHIFT 0 /* LPC_IO_DEC[2:0] */
+#define COM_DEC_MASK 7
+#define COM_DEC_3F8 0 /* 3F8h - 3FFh (COM1) */
+#define COM_DEC_2F8 1 /* 2F8h - 2FFh (COM2) */
+#define COM_DEC_220 2 /* 220h - 227h */
+#define COM_DEC_228 3 /* 228h - 22Fh */
+#define COM_DEC_238 4 /* 238h - 23Fh */
+#define COM_DEC_2E8 5 /* 2E8h - 2EFh (COM4) */
+#define COM_DEC_338 6 /* 338h - 33Fh */
+#define COM_DEC_3E8 7 /* 3E8h - 3EFh (COM3) */
+#define LPC_EN 0x82 /* LPC IF Enables Register */
+#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
+#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
+#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
+#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
+#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
+#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
+#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
+#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
+#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
+#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */
+#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
+#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
+#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
+
+#endif /* _DENVERTON_NS_LPC_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h
new file mode 100644
index 0000000000..4d1ac70c3a
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/msr.h
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_MSR_H_
+#define _DENVERTON_NS_MSR_H_
+
+#define MSR_PLATFORM_ID 0x17
+#define MSR_PIC_MSG_CONTROL 0x2e
+#define CORE_THREAD_COUNT_MSR 0x35
+#define IA32_FEATURE_CONTROL 0x3a
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+#define MSR_PLATFORM_INFO 0xce
+#define PLATFORM_INFO_SET_TDP (1 << 29)
+#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PMG_IO_CAPTURE_BASE 0xe4
+#define MSR_FEATURE_CONFIG 0x13c
+#define SMM_MCA_CAP_MSR 0x17d
+#define SMM_CPU_SVRSTR_BIT 57
+#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
+#define MSR_FLEX_RATIO 0x194
+#define FLEX_RATIO_LOCK (1 << 20)
+#define FLEX_RATIO_EN (1 << 16)
+#define IA32_MISC_ENABLE 0x1a0
+#define MSR_MISC_PWR_MGMT 0x1aa
+#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
+#define MSR_TURBO_RATIO_LIMIT 0x1ad
+#define MSR_TEMPERATURE_TARGET 0x1a2
+#define IA32_PERF_CTL 0x199
+#define IA32_THERM_INTERRUPT 0x19b
+#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
+#define ENERGY_POLICY_PERFORMANCE 0
+#define ENERGY_POLICY_NORMAL 6
+#define ENERGY_POLICY_POWERSAVE 15
+#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
+#define EMRR_PHYS_BASE_MSR 0x1f4
+#define EMRR_PHYS_MASK_MSR 0x1f5
+#define IA32_PLATFORM_DCA_CAP 0x1f8
+#define MSR_POWER_CTL 0x1fc
+#define MSR_LT_LOCK_MEMORY 0x2e7
+#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4
+#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5
+#define IA32_MC0_STATUS 0x401
+#define SMM_FEATURE_CONTROL_MSR 0x4e0
+#define SMM_CPU_SAVE_EN (1 << 1)
+
+#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a
+#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b
+#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c
+#define MSR_C_STATE_LATENCY_CONTROL_3 0x633
+#define MSR_C_STATE_LATENCY_CONTROL_4 0x634
+#define MSR_C_STATE_LATENCY_CONTROL_5 0x635
+#define IRTL_VALID (1 << 15)
+#define IRTL_1_NS (0 << 10)
+#define IRTL_32_NS (1 << 10)
+#define IRTL_1024_NS (2 << 10)
+#define IRTL_32768_NS (3 << 10)
+#define IRTL_1048576_NS (4 << 10)
+#define IRTL_33554432_NS (5 << 10)
+#define IRTL_RESPONSE_MASK (0x3ff)
+#define MSR_COUNTER_24_MHZ 0x637
+
+/* long duration in low dword, short duration in high dword */
+#define MSR_PKG_POWER_LIMIT 0x610
+#define PKG_POWER_LIMIT_MASK 0x7fff
+#define PKG_POWER_LIMIT_EN (1 << 15)
+#define PKG_POWER_LIMIT_CLAMP (1 << 16)
+#define PKG_POWER_LIMIT_TIME_SHIFT 17
+#define PKG_POWER_LIMIT_TIME_MASK 0x7f
+
+#define MSR_VR_CURRENT_CONFIG 0x601
+#define MSR_VR_MISC_CONFIG 0x603
+#define MSR_PKG_POWER_SKU_UNIT 0x606
+#define MSR_PKG_POWER_SKU 0x614
+#define MSR_DDR_RAPL_LIMIT 0x618
+#define MSR_VR_MISC_CONFIG2 0x636
+#define MSR_PP0_POWER_LIMIT 0x638
+#define MSR_PP1_POWER_LIMIT 0x640
+
+#define MSR_CONFIG_TDP_NOMINAL 0x648
+#define MSR_CONFIG_TDP_LEVEL1 0x649
+#define MSR_CONFIG_TDP_LEVEL2 0x64a
+#define MSR_CONFIG_TDP_CONTROL 0x64b
+#define MSR_TURBO_ACTIVATION_RATIO 0x64c
+
+/* SMM save state MSRs */
+#define SMBASE_MSR 0xc20
+#define IEDBASE_MSR 0xc22
+
+/* MTRRcap_MSR bits */
+#define SMRR_SUPPORTED (1 << 11)
+#define PRMRR_SUPPORTED (1 << 12)
+
+/* IA32_MISC_ENABLE bits */
+#define SPEED_STEP_ENABLE_BIT (1 << 16)
+
+/* Read BCLK from MSR */
+unsigned int bus_freq_khz(void);
+
+#endif /* _DENVERTON_NS_MSR_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h
new file mode 100644
index 0000000000..cf10823ca1
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/nvs.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 - 2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_NVS_H_
+#define _DENVERTON_NS_NVS_H_
+
+typedef struct {
+ /* Miscellaneous */
+ u16 osys; /* 0x00 - Operating System */
+ u8 smif; /* 0x02 - SMI function call ("TRAP") */
+ u8 prm0; /* 0x03 - SMI function call parameter */
+ u8 prm1; /* 0x04 - SMI function call parameter */
+ u8 scif; /* 0x05 - SCI function call (via _L00) */
+ u8 prm2; /* 0x06 - SCI function call parameter */
+ u8 prm3; /* 0x07 - SCI function call parameter */
+ u8 lckf; /* 0x08 - Global Lock function for EC */
+ u8 prm4; /* 0x09 - Lock function parameter */
+ u8 prm5; /* 0x0a - Lock function parameter */
+ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
+ u8 lids; /* 0x0f - LID state (open = 1) */
+ u8 pwrs; /* 0x10 - Power state (AC = 1) */
+ u8 pcnt; /* 0x11 - Processor Count */
+ u8 tpmp; /* 0x12 - TPM Present and Enabled */
+ u8 tlvl; /* 0x13 - Throttle Level */
+ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */
+ u8 rsvd1[11];
+
+ /* Device Config */
+ u8 s5u0; /* 0x20 - Enable USB0 in S5 */
+ u8 s5u1; /* 0x21 - Enable USB1 in S5 */
+ u8 s3u0; /* 0x22 - Enable USB0 in S3 */
+ u8 s3u1; /* 0x23 - Enable USB1 in S3 */
+ u8 tact; /* 0x24 - Thermal Active trip point */
+ u8 tpsv; /* 0x25 - Thermal Passive trip point */
+ u8 tcrt; /* 0x26 - Thermal Critical trip point */
+ u8 dpte; /* 0x27 - Enable DPTF */
+ u8 rsvd2[8];
+
+ /* Base Addresses */
+ u32 obsolete_cmem; /* 0x30 - CBMEM TOC */
+ u32 tolm; /* 0x34 - Top of Low Memory */
+ u32 cbmc; /* 0x38 - coreboot memconsole */
+ u32 mmiob; /* 0x3c - MMIO Base Low */
+ u32 mmiol; /* 0x40 - MMIO Base Limit */
+ u64 mmiohb; /* 0x44 - MMIO Base High */
+ u64 mmiohl; /* 0x4c - MMIO Base Limit */
+ u32 tsegb; /* 0x54 - TSEG Base Low */
+ u32 tsegl; /* 0x58 - TSEG Length/Size */
+ u8 rsvd3[164];
+
+} __attribute__((packed)) global_nvs_t;
+
+void acpi_create_gnvs(global_nvs_t *gnvs);
+#ifdef __SMM__
+/* Used in SMM to find the ACPI GNVS address */
+global_nvs_t *smm_get_gnvs(void);
+#endif
+
+#endif /* _DENVERTON_NS_NVS_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/p2sb.h b/src/soc/intel/denverton_ns/include/soc/p2sb.h
new file mode 100644
index 0000000000..6d5a41528a
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/p2sb.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_P2SB_H_
+#define _DENVERTON_NS_P2SB_H_
+
+/* Generate MP-table IRQ numbers for PCI devices. */
+#define IO_APIC0 1
+
+/* P2SB Bridge Registers (D31:F1) */
+#define PCH_P2SB_DEV PCI_DEV(0, P2SB_DEV, P2SB_FUNC)
+
+/* IO/MEM BARs */
+#define SBREG_LO 0x10
+#define MASK_SBREG_LO 0xff000000
+#define SBREG_HI 0x14
+#define MASK_SBREG_HI 0xffffffff
+
+/* ITSS PCRs (PID:ITSS) */
+#define PCR_ITSS_PIRQA_ROUT 0x3100
+#define PCR_ITSS_PIRQB_ROUT 0x3101
+#define PCR_ITSS_PIRQC_ROUT 0x3102
+#define PCR_ITSS_PIRQD_ROUT 0x3103
+#define PCR_ITSS_PIRQE_ROUT 0x3104
+#define PCR_ITSS_PIRQF_ROUT 0x3105
+#define PCR_ITSS_PIRQG_ROUT 0x3106
+#define PCR_ITSS_PIRQH_ROUT 0x3107
+
+#define PCR_ITSS_PIR00 0x3140
+#define PCR_ITSS_PIR01 0x3142
+#define PCR_ITSS_PIR02 0x3144
+#define PCR_ITSS_PIR03 0x3146
+#define PCR_ITSS_PIR04 0x3148
+#define PCR_ITSS_PIR05 0x314A
+#define PCR_ITSS_PIR06 0x314C
+#define PCR_ITSS_PIR07 0x314E
+#define PCR_ITSS_PIR08 0x3150
+#define PCR_ITSS_PIR09 0x3152
+#define PCR_ITSS_PIR10 0x3154
+#define PCR_ITSS_PIR11 0x3156
+#define PCR_ITSS_PIR12 0x3158
+
+#define PCH_PCR_ITSS_GIC 0x31FC ///< General Interrupt Control
+///< Max IRQ entry size, 1 = 24 entry size, 0 = 120 entry size
+#define PCH_PCR_ITSS_GIC_MAX_IRQ_24 \
+ (1 << 9)
+#define PCH_PCR_ITSS_GIC_AME (1 << 17) ///< Alternate Access Mode Enable
+#define PCH_PCR_ITSS_GIC_SPS (1 << 16) ///< Shutdown Policy Select
+#define PCH_PCR_ITSS_IPC0 0x3200 ///< Interrupt Polarity Control 0
+#define PCH_PCR_ITSS_IPC1 0x3204 ///< Interrupt Polarity Control 1
+#define PCH_PCR_ITSS_IPC2 0x3208 ///< Interrupt Polarity Control 2
+#define PCH_PCR_ITSS_IPC3 0x320C ///< Interrupt Polarity Control 3
+
+#endif /* _DENVERTON_NS_P2SB_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/pattrs.h b/src/soc/intel/denverton_ns/include/soc/pattrs.h
new file mode 100644
index 0000000000..b558e24afe
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/pattrs.h
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_PATTRS_H_
+#define _DENVERTON_NS_PATTRS_H_
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+
+enum { IACORE_MIN, IACORE_LFM, IACORE_MAX, IACORE_TURBO, IACORE_END };
+
+/* The pattrs structure is a common place to stash pertinent information
+ * about the processor or platform. Instead of going to the source (msrs, cpuid)
+ * every time an attribute is needed use the pattrs structure.
+ */
+struct pattrs {
+ msr_t platform_id;
+ msr_t platform_info;
+ int iacore_ratios[IACORE_END];
+ int iacore_vids[IACORE_END];
+ uint32_t cpuid;
+ int revid;
+ int stepping;
+ const void *microcode_patch;
+ int address_bits;
+ int num_cpus;
+ unsigned int bclk_khz;
+};
+
+/* This is just to hide the abstraction w/o relying on how the underlying
+ * storage is allocated. */
+#define PATTRS_GLOB_NAME __global_pattrs
+#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME
+extern DEFINE_PATTRS;
+
+static inline const struct pattrs *pattrs_get(void)
+{
+ return &PATTRS_GLOB_NAME;
+}
+
+#endif /* _DENVERTON_NS_PATTRS_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
new file mode 100644
index 0000000000..138b6f6081
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
@@ -0,0 +1,204 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_PCI_DEVS_H_
+#define _DENVERTON_NS_PCI_DEVS_H_
+
+/* All these devices live on bus 0 with the associated device and function */
+
+#include <rules.h>
+
+#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_##slot, 0)
+#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func)
+
+#if ENV_RAMSTAGE
+#include <device/device.h>
+#include <device/pci_def.h>
+#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
+#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
+#else
+#include <arch/io.h>
+#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_##slot, 0)
+#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func)
+#endif
+
+/* SoC transaction router */
+#define SA_DEV 0x0
+#define SA_FUNC 0
+#define SA_DEVID 0x1980
+#define SOC_DEV SA_DEV
+#define SOC_FUNC SA_FUNC
+#define SOC_DEVID SA_DEVID
+
+/* RAS */
+#define RAS_DEV 0x4
+#define RAS_FUNC 0
+#define RAS_DEVID 0x19a1
+
+/* Root Complex Event Collector */
+#define RCEC_DEV 0x5
+#define RCEC_FUNC 0
+#define RCEC_DEVID 0x19a2
+
+/* Virtual Root Port 2 */
+#define VRP2_DEV 0x6
+#define VRP2_FUNC 0
+#define VRP2_DEVID 0x19a3
+
+/* PCIe Root Ports */
+#define PCIE_DEV 0x09
+#define MAX_PCIE_PORT 0x8
+#define PCIE_PORT1_DEV 0x09
+#define PCIE_PORT1_FUNC 0
+#define PCIE_PORT1_DEVID 0x19a4
+#define PCIE_PORT2_DEV 0x0a
+#define PCIE_PORT2_FUNC 0
+#define PCIE_PORT2_DEVID 0x19a5
+#define PCIE_PORT3_DEV 0x0b
+#define PCIE_PORT3_FUNC 0
+#define PCIE_PORT3_DEVID 0x19a6
+#define PCIE_PORT4_DEV 0x0c
+#define PCIE_PORT4_FUNC 0
+#define PCIE_PORT4_DEVID 0x19a7
+#define PCIE_PORT5_DEV 0x0e
+#define PCIE_PORT5_FUNC 0
+#define PCIE_PORT5_DEVID 0x19a8
+#define PCIE_PORT6_DEV 0x0f
+#define PCIE_PORT6_FUNC 0
+#define PCIE_PORT6_DEVID 0x19a9
+#define PCIE_PORT7_DEV 0x10
+#define PCIE_PORT7_FUNC 0
+#define PCIE_PORT7_DEVID 0x19aa
+#define PCIE_PORT8_DEV 0x11
+#define PCIE_PORT8_FUNC 0
+#define PCIE_PORT8_DEVID 0x19ab
+
+/* SMBUS 2 */
+#define SMBUS2_DEV 0x12
+#define SMBUS2_FUNC 0
+#define SMBUS2_DEVID 0x19ac
+
+/* SATA */
+#define SATA_DEV 0x13
+#define SATA_FUNC 0
+#define AHCI_DEVID 0x19b2
+#define SATA2_DEV 0x14
+#define SATA2_FUNC 0
+#define AHCI2_DEVID 0x19c2
+
+/* xHCI */
+#define XHCI_DEV 0x15
+#define XHCI_FUNC 0
+#define XHCI_DEVID 0x19d0
+
+/* Virtual Root Port 0 */
+#define VRP0_DEV 0x16
+#define VRP0_FUNC 0
+#define VRP0_DEVID 0x19d1
+
+/* Virtual Root Port 1 */
+#define VRP1_DEV 0x17
+#define VRP1_FUNC 0
+#define VRP1_DEVID 0x19d2
+
+/* CSME */
+#define ME_HECI_DEV 0x18
+#define ME_HECI1_DEV ME_HECI_DEV
+#define ME_HECI1_FUNC 0
+#define ME_HECI1_DEVID 0x19d3
+#define ME_HECI2_DEV ME_HECI_DEV
+#define ME_HECI2_FUNC 1
+#define ME_HECI2_DEVID 0x19d4
+#define ME_IEDR_DEV ME_HECI_DEV
+#define ME_IEDR_FUNC 2
+#define ME_IEDR_DEVID 0x19ea
+#define ME_MEKT_DEV ME_HECI_DEV
+#define ME_MEKT_FUNC 3
+#define ME_MEKT_DEVID 0x19d5
+#define ME_HECI3_DEV ME_HECI_DEV
+#define ME_HECI3_FUNC 4
+#define ME_HECI3_DEVID 0x19d6
+
+/* HSUART */
+#define HSUART_DEV 0x1a
+#define HSUART_DEVID 0x19d8
+#define HSUART1_DEV HSUART_DEV
+#define HSUART1_FUNC 0
+#define HSUART1_DEVID HSUART_DEVID
+#define HSUART2_DEV HSUART_DEV
+#define HSUART2_FUNC 1
+#define HSUART2_DEVID HSUART_DEVID
+#define HSUART3_DEV HSUART_DEV
+#define HSUART3_FUNC 2
+#define HSUART3_DEVID HSUART_DEVID
+
+/* IE */
+#define IE_HECI_DEV 0x1b
+#define IE_HECI1_DEV IE_HECI_DEV
+#define IE_HECI1_FUNC 0
+#define IE_HECI1_DEVID 0x19e5
+#define IE_HECI2_DEV IE_HECI_DEV
+#define IE_HECI2_FUNC 1
+#define IE_HECI2_DEVID 0x19e6
+#define IE_IEDR_DEV IE_HECI_DEV
+#define IE_IEDR_FUNC 2
+#define IE_IEDR_DEVID 0x19e7
+#define IE_MEKT_DEV IE_HECI_DEV
+#define IE_MEKT_FUNC 3
+#define IE_MEKT_DEVID 0x19e8
+#define IE_HECI3_DEV IE_HECI_DEV
+#define IE_HECI3_FUNC 4
+#define IE_HECI3_DEVID 0x19e9
+
+/* MMC Port */
+#define MMC_DEV 0x1c
+#define MMC_FUNC 0
+#define MMC_DEVID 0x19db
+
+/* Platform Controller Unit */
+#define PCU_DEV 0x1f
+#define LPC_DEV PCU_DEV
+#define LPC_FUNC 0
+#define LPC_DEVID 0x19dc
+#define P2SB_DEV PCU_DEV
+#define P2SB_FUNC 1
+#define P2SB_DEVID 0x19dd
+#define PMC_DEV PCU_DEV
+#define PMC_FUNC 2
+#define PMC_DEVID 0x19de
+#define SMBUS_DEV PCU_DEV
+#define SMBUS_FUNC 4
+#define SMBUS_DEVID 0x19df
+#define SPI_DEV PCU_DEV
+#define SPI_FUNC 5
+#define SPI_DEVID 0x19e0
+#define NPK_DEV PCU_DEV
+#define NPK_FUNC 7
+#define NPK_DEVID 0x19e1
+
+/* TODO - New added */
+#define SA_DEV_SLOT_ROOT 0x00
+#define SA_DEVFN_ROOT _SA_DEVFN(ROOT)
+#define SA_DEV_ROOT _SA_DEV(ROOT)
+
+#define PCH_DEV_SLOT_LPC 0x1f
+#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
+#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
+#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
+#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
+
+#endif /* _DENVERTON_NS_PCI_DEVS_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/pcr.h b/src/soc/intel/denverton_ns/include/soc/pcr.h
new file mode 100644
index 0000000000..601577640b
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/pcr.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_PCR_H_
+#define _DENVERTON_NS_PCR_H_
+
+/* PCR BASE */
+#include <soc/iomap.h>
+
+/* PCR address */
+#define PCH_PCR_ADDRESS(Pid, Offset) \
+ (DEFAULT_PCR_BASE | ((uint8_t)(Pid) << 16) | (uint16_t)(Offset))
+
+/* PID for PCR and SBI */
+typedef enum {
+ PID_SMB = 0xCF,
+ PID_ITSS = 0xD0,
+ PID_GPIOCOM0 = 0xC2,
+ PID_GPIOCOM1 = 0xC5,
+} PCH_SBI_PID;
+
+#endif /* _DENVERTON_NS_PCR_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h
new file mode 100644
index 0000000000..2dc8781804
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/pm.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_PM_H_
+#define _DENVERTON_NS_PM_H_
+
+#include <arch/io.h>
+#include <soc/pmc.h>
+
+#define SLEEP_STATE_S0 0
+#define SLEEP_STATE_S3 3
+#define SLEEP_STATE_S5 5
+
+struct chipset_power_state {
+ uint16_t pm1_sts;
+ uint16_t pm1_en;
+ uint32_t pm1_cnt;
+ uint16_t tco1_sts;
+ uint16_t tco2_sts;
+ uint32_t gpe0_sts[4];
+ uint32_t gpe0_en[4];
+ uint32_t gen_pmcon_a;
+ uint32_t gen_pmcon_b;
+ uint32_t gblrst_cause[2];
+ uint32_t prev_sleep_state;
+} __attribute__((packed));
+
+struct chipset_power_state *fill_power_state(void);
+
+/* Power Management Utility Functions. */
+uint32_t clear_smi_status(void);
+uint16_t clear_pm1_status(void);
+uint32_t clear_tco_status(void);
+uint32_t clear_gpe_status(void);
+void clear_pmc_status(void);
+void enable_smi(uint32_t mask);
+void disable_smi(uint32_t mask);
+void enable_pm1(uint16_t events);
+void enable_pm1_control(uint32_t mask);
+void disable_pm1_control(uint32_t mask);
+void enable_gpe(uint32_t mask);
+void disable_gpe(uint32_t mask);
+void disable_all_gpe(void);
+
+#endif /* _DENVERTON_NS_PM_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h
new file mode 100644
index 0000000000..edb5c55df6
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/pmc.h
@@ -0,0 +1,255 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_PMC_H_
+#define _DENVERTON_NS_PMC_H_
+
+/* PCI Configuration Space (D31:F2): PMC/ACPI */
+#define PCH_PMC_DEV PCI_DEV(0, PMC_DEV, PMC_FUNC)
+
+/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
+#define PMC_ACPI_BASE 0x40 /* IO BAR */
+#define MASK_PMC_ACPI_BASE 0xfffc
+#define PMC_ACPI_CNT 0x44
+#define PMC_ACPI_CNT_PWRM_EN (1 << 8) /* PWRM enable */
+#define PMC_ACPI_CNT_ACPI_EN (1 << 7) /* ACPI eanble */
+#define PMC_ACPI_CNT_SCIS ((1 << 2) | (1 << 1) | (1 << 0)) /* SCI IRQ select \
+ */
+#define PMC_ACPI_CNT_SCIS_MASK 0x07
+#define PMC_ACPI_CNT_SCIS_IRQ9 0x00
+#define PMC_ACPI_CNT_SCIS_IRQ10 0x01
+#define PMC_ACPI_CNT_SCIS_IRQ11 0x02
+#define PMC_ACPI_CNT_SCIS_DISABLE 0x03
+#define PMC_ACPI_CNT_SCIS_IRQ20 0x04
+#define PMC_ACPI_CNT_SCIS_IRQ21 0x05
+#define PMC_ACPI_CNT_SCIS_IRQ22 0x06
+#define PMC_ACPI_CNT_SCIS_IRQ23 0x07
+#define PMC_PWRM_BASE 0x48 /* MEM BAR */
+#define MASK_PMC_PWRM_BASE 0xfffff000 /* 4K alignment */
+#define PMC_GEN_PMCON_A 0xA0
+#define PMC_GEN_PMCON_B 0xA4
+#define PMC_GEN_PMCON_B_RTC_PWR_STS 0x04
+#define PMC_GEN_PMCON_B_PWR_FLR 0x02
+#define PMC_GEN_PMCON_B_AFTERG3_EN 0x00
+#define PMC_ETR3 0xAC
+#define PMC_ETR3_CF9LOCK BIT31 ///< CF9h Lockdown
+#define PMC_ETR3_CF9GR BIT20 ///< CF9h Global Reset
+
+/* IO Mapped registers behind ACPI_BASE_ADDRESS */
+#define PM1_STS 0x00
+#define WAK_STS (1 << 15)
+#define PCIEXPWAK_STS (1 << 14)
+#define PRBTNOR_STS (1 << 11)
+#define RTC_STS (1 << 10)
+#define PWRBTN_STS (1 << 8)
+#define GBL_STS (1 << 5)
+#define BM_STS (1 << 4)
+#define TMROF_STS (1 << 0)
+#define PM1_EN 0x02
+#define PCIEXPWAK_DIS (1 << 14)
+#define RTC_EN (1 << 10)
+#define PWRBTN_EN (1 << 8)
+#define GBL_EN (1 << 5)
+#define TMROF_EN (1 << 0)
+#define PM1_CNT 0x04
+#define SLP_EN (1 << 13)
+#define SLP_TYP_SHIFT 10
+#define SLP_TYP (7 << SLP_TYP_SHIFT)
+#define SLP_TYP_S0 0
+#define SLP_TYP_S1 1
+#define SLP_TYP_S3 5
+#define SLP_TYP_S4 6
+#define SLP_TYP_S5 7
+#define GBL_RLS (1 << 2)
+#define BM_RLD (1 << 1)
+#define SCI_EN (1 << 0)
+#define PM1_TMR 0x08
+#define SMI_EN 0x30
+#define LEGACY_USB3_EN (1 << 31) // Legacy USB3 SMI logic
+#define GPIO_UNLOCK_EN (1 << 27) // GPIO unlock SMI
+#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
+#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
+#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
+#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
+#define MCSMI_EN (1 << 11) // Trap microcontroller range access
+#define BIOS_RLS (1 << 7) // asserts SCI on bit set
+#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
+#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
+#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
+#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
+#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
+#define EOS (1 << 1) // End of SMI (deassert SMI#)
+#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
+#define SMI_STS 0x34
+#define SMI_STS_LEGACY_USB3 (1 << 31)
+#define SMI_STS_GPIO_UNLOCK (1 << 27)
+#define SMI_STS_SPI (1 << 26)
+#define SMI_STS_MONITOR (1 << 21)
+#define SMI_STS_PCI_EXP (1 << 20)
+#define SMI_STS_PATCH (1 << 19)
+#define SMI_STS_INTEL_USB2 (1 << 18)
+#define SMI_STS_LEGACY_USB2 (1 << 17)
+#define SMI_STS_SMBUS (1 << 16)
+#define SMI_STS_SERIRQ (1 << 15)
+#define SMI_STS_PERIODIC (1 << 14)
+#define SMI_STS_TCO (1 << 13)
+#define SMI_STS_DEVMON (1 << 12)
+#define SMI_STS_MCSMI (1 << 11)
+#define SMI_STS_GPE1 (1 << 10)
+#define SMI_STS_GPE0 (1 << 9)
+#define SMI_STS_PM1 (1 << 8)
+#define SMI_STS_SWSMI_TMR (1 << 6)
+#define SMI_STS_APMC (1 << 5)
+#define SMI_STS_SLP_SMI (1 << 4)
+#define SMI_STS_LEGACY_USB (1 << 3)
+#define SMI_STS_BIOS (1 << 2)
+#define GPE_CTRL 0x40
+#define SWGPE_CTRL (1 << 17)
+#define PM2_CNT 0x50
+#define GPE0_STS 0x80
+#define GPIO31_STS (1 << 31)
+#define GPIO30_STS (1 << 30)
+#define GPIO29_STS (1 << 29)
+#define GPIO28_STS (1 << 28)
+#define GPIO27_STS (1 << 27)
+#define GPIO26_STS (1 << 26)
+#define GPIO25_STS (1 << 25)
+#define GPIO24_STS (1 << 24)
+#define GPIO23_STS (1 << 23)
+#define GPIO22_STS (1 << 22)
+#define GPIO21_STS (1 << 21)
+#define GPIO20_STS (1 << 20)
+#define GPIO19_STS (1 << 19)
+#define GPIO18_STS (1 << 18)
+#define GPIO17_STS (1 << 17)
+#define GPIO16_STS (1 << 16)
+#define GPIO15_STS (1 << 15)
+#define GPIO14_STS (1 << 14)
+#define GPIO13_STS (1 << 13)
+#define GPIO12_STS (1 << 12)
+#define GPIO11_STS (1 << 11)
+#define GPIO10_STS (1 << 10)
+#define GPIO09_STS (1 << 09)
+#define GPIO08_STS (1 << 08)
+#define GPIO07_STS (1 << 07)
+#define GPIO06_STS (1 << 06)
+#define GPIO05_STS (1 << 05)
+#define GPIO04_STS (1 << 04)
+#define GPIO03_STS (1 << 03)
+#define GPIO02_STS (1 << 02)
+#define GPIO01_STS (1 << 01)
+#define GPIO00_STS (1 << 00)
+#define GPE0_STS_63_32 0x84
+#define GPE0_STS_95_64 0x88
+#define GPE0_STS_127_96 0x8c
+#define PME_B0_STS (1 << 13)
+#define ME_SCI_STS (1 << 12)
+#define PME_STS (1 << 11)
+#define PCI_EXP_STS (1 << 9)
+#define RI_STS (1 << 8)
+#define SMB_WAK_STS (1 << 7)
+#define TCOSCI_STS (1 << 6)
+#define IE_SCI_STS (1 << 3)
+#define SWGPE_STS (1 << 2)
+#define HOT_PLUG_STS (1 << 1)
+#define GPE0_EN 0x90
+#define GPIO31_EN (1 << 31)
+#define GPIO30_EN (1 << 30)
+#define GPIO29_EN (1 << 29)
+#define GPIO28_EN (1 << 28)
+#define GPIO27_EN (1 << 27)
+#define GPIO26_EN (1 << 26)
+#define GPIO25_EN (1 << 25)
+#define GPIO24_EN (1 << 24)
+#define GPIO23_EN (1 << 23)
+#define GPIO22_EN (1 << 22)
+#define GPIO21_EN (1 << 21)
+#define GPIO20_EN (1 << 20)
+#define GPIO19_EN (1 << 19)
+#define GPIO18_EN (1 << 18)
+#define GPIO17_EN (1 << 17)
+#define GPIO16_EN (1 << 16)
+#define GPIO15_EN (1 << 15)
+#define GPIO14_EN (1 << 14)
+#define GPIO13_EN (1 << 13)
+#define GPIO12_EN (1 << 12)
+#define GPIO11_EN (1 << 11)
+#define GPIO10_EN (1 << 10)
+#define GPIO09_EN (1 << 09)
+#define GPIO08_EN (1 << 08)
+#define GPIO07_EN (1 << 07)
+#define GPIO06_EN (1 << 06)
+#define GPIO05_EN (1 << 05)
+#define GPIO04_EN (1 << 04)
+#define GPIO03_EN (1 << 03)
+#define GPIO02_EN (1 << 02)
+#define GPIO01_EN (1 << 01)
+#define GPIO00_EN (1 << 00)
+#define GPE0_EN_63_32 0x94
+#define GPE0_EN_95_64 0x98
+#define GPE0_EN_127_96 0x9c
+#define PME_B0_EN (1 << 13)
+#define ME_SCI_EN (1 << 12)
+#define PME_EN (1 << 11)
+#define PCI_EXP_EN (1 << 9)
+#define RI_EN (1 << 8)
+#define SMB_WAK_EN (1 << 7)
+#define TCOSCI_EN (1 << 6)
+#define IE_SCI_EN (1 << 3)
+#define SWGPE_EN (1 << 2)
+#define HOT_PLUG_EN (1 << 1)
+
+/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
+#define TCO_RLD 0x00
+#define TCO1_STS 0x04
+#define TCO1_STS_TCO_SLVSEL (1 << 13)
+#define TCO1_STS_CPUSERR (1 << 12)
+#define TCO1_STS_CPUSMI (1 << 10)
+#define TCO1_STS_CPUSCI (1 << 9)
+#define TCO1_STS_BIOSWR (1 << 8)
+#define TCO1_STS_NEWCENTURY (1 << 7)
+#define TCO1_STS_TIMEOUT (1 << 3)
+#define TCO1_STS_TCO_INT (1 << 2)
+#define TCO1_STS_OS_TCO_SMI (1 << 1)
+#define TCO1_STS_NMI2SMI (1 << 0)
+#define TCO2_STS 0x06
+#define TCO2_STS_SMLINK_SLAVE_SMI 0x04
+#define TCO2_STS_SECOND_TO 0x02
+#define TCO2_STS_INTRD_DET 0x01
+#define TCO1_CNT 0x08
+#define TCO_LOCK (1 << 12)
+#define TCO_TMR_HLT (1 << 11)
+#define TCO2_CNT 0x0a
+#define TCO_TMR 0x12
+
+/* I/O ports */
+#define RST_CNT 0xcf9
+#define FULL_RST (1 << 3)
+#define RST_CPU (1 << 2)
+#define SYS_RST (1 << 1)
+
+#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
+
+#if IS_ENABLED(CONFIG_ELOG)
+void southcluster_log_state(void);
+#else
+static inline void southcluster_log_state(void) {}
+#endif
+
+#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
+
+#endif /* _DENVERTON_NS_PMC_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/ramstage.h b/src/soc/intel/denverton_ns/include/soc/ramstage.h
new file mode 100644
index 0000000000..63ed4327f2
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/ramstage.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DENVERTON_NS_SOC_RAMSTAGE_H_
+#define _DENVERTON_NS_SOC_RAMSTAGE_H_
+
+#include <device/device.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <soc/intel/common/opregion.h>
+
+void denverton_init_cpus(device_t dev);
+void mainboard_silicon_init_params(FSPS_UPD *params);
+void southcluster_enable_dev(device_t dev);
+
+extern struct pci_operations soc_pci_ops;
+
+#endif
diff --git a/src/soc/intel/denverton_ns/include/soc/romstage.h b/src/soc/intel/denverton_ns/include/soc/romstage.h
new file mode 100644
index 0000000000..2c6c5ce890
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/romstage.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 - 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _SOC_DENVERTON_NS_ROMSTAGE_H_
+#define _SOC_DENVERTON_NS_ROMSTAGE_H_
+
+#include <arch/cpu.h>
+#include <fsp/api.h>
+
+/* These functions are weak and can be overridden by a mainboard functions. */
+void mainboard_memory_init_params(FSPM_UPD *mupd);
+void mainboard_config_gpios(void);
+
+#endif /* _SOC_DENVERTON_NS_ROMSTAGE_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/sata.h b/src/soc/intel/denverton_ns/include/soc/sata.h
new file mode 100644
index 0000000000..afa39b5d65
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/sata.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_SATA_H
+#define _DENVERTON_NS_SATA_H
+
+/* PCI Configuration Space (D19:F0): SATA #0 */
+/* PCI Configuration Space (D20:F0): SATA #1 */
+#define PCH_SATA0_DEV PCI_DEV(0, SATA_DEV, SATA_FUNC)
+#define PCH_SATA1_DEV PCI_DEV(0, SATA2_DEV, SATA2_FUNC)
+
+#define SATA_MAP 0x90
+#define SATA_MAP_AHCI (0 << 6)
+#define SATA_MAP_RAID (1 << 6)
+#define SATA_PSC 0x92
+
+#endif //_DENVERTON_NS_SATA_H
diff --git a/src/soc/intel/denverton_ns/include/soc/smbus.h b/src/soc/intel/denverton_ns/include/soc/smbus.h
new file mode 100644
index 0000000000..5dbeecc0cf
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/smbus.h
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DENVERTON_NS_SMBUS_H_
+#define _DENVERTON_NS_SMBUS_H_
+
+/* PCI Configuration Space (D31:F4): SMBus */
+#define SMB_BASE 0x20
+#define HOSTC 0x40
+#define HST_EN (1 << 0)
+#define HOSTC_SMI_EN (1 << 1)
+#define HOSTC_I2C_EN (1 << 2)
+#define SMB_RCV_SLVA 0x09
+/* SMBUS TCO base address. */
+#define TCOBASE 0x50
+#define MASK_TCOBASE 0xffe0
+#define TCOCTL 0x54
+#define TCOBASE_EN (1 << 8)
+#define TCOBASE_LOCK (1 << 0)
+
+/* SMBus I/O bits. */
+#define SMBHSTSTAT 0x0
+#define HST_HBSY (1 << 0)
+#define HST_INTR (1 << 1)
+#define HST_DERR (1 << 2)
+#define HST_BERR (1 << 3)
+#define HST_BYTE_DONE_STS (1 << 7)
+#define HST_HSTS_ALL 0xFF
+#define SMBHSTCTL 0x2
+#define HST_LAST_BYTE (1 << 5)
+#define HST_START (1 << 6)
+#define HST_CMD_IIC_READ 0x18
+#define HST_READ 0x01 // RW
+#define SMBHSTCMD 0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT 0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMBHSTAUXC 0xd
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL 0xf
+
+/*
+ * SMBus Private Config Registers (PID:SMB)
+ */
+#define PCR_SMBUS_TCOCFG 0x00 /* TCO Configuration register */
+#define PCR_SMBUS_TCOCFG_IE (1 << 7) /* TCO IRQ Enable */
+#define PCR_SMBUS_TCOCFG_IS 7 /* TCO IRQ Select */
+#define PCR_SMBUS_TCOCFG_IRQ_9 0x00
+#define PCR_SMBUS_TCOCFG_IRQ_10 0x01
+#define PCR_SMBUS_TCOCFG_IRQ_11 0x02
+#define PCR_SMBUS_TCOCFG_IRQ_20 0x04 /* only if APIC enabled */
+#define PCR_SMBUS_TCOCFG_IRQ_21 0x05 /* only if APIC enabled */
+#define PCR_SMBUS_TCOCFG_IRQ_22 0x06 /* only if APIC enabled */
+#define PCR_SMBUS_TCOCFG_IRQ_23 0x07 /* only if APIC enabled */
+#define PCR_SMBUS_SMBTM 0x04 /* SMBus Test Mode */
+#define PCR_SMBUS_SMBTM_SMBCT (1 << 1) /* SMBus Counter */
+#define PCR_SMBUS_SMBTM_SMBDG (1 << 0) /* SMBus Deglitch */
+#define PCR_SMBUS_SCTM 0x08 /* Short Counter Test Mode */
+#define PCR_SMBUS_SCTM_SSU (1 << 31) /* Simulation Speed-Up */
+#define PCR_SMBUS_GC 0x0C /* General Control */
+#define PCR_SMBUS_GC_FD (1 << 0) /* Function Disable */
+#define PCR_SMBUS_GC_NR (1 << 1) /* No Reboot */
+#define PCR_SMBUS_GC_SMBSCGE (1 << 2) /* SMB Static Clock Gating Enable */
+#define PCR_SMBUS_PCE 0x10 /* Power Control Enable */
+#define PCR_SMBUS_PCE_HAE (1 << 5) /* Hardware Autonomous Enable */
+
+#endif /* _DENVERTON_NS_SMBUS_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h
new file mode 100644
index 0000000000..fe6dc826d1
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/smm.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_SMM_H_
+#define _DENVERTON_NS_SMM_H_
+
+struct smm_relocation_attrs {
+ uint32_t smbase;
+ uint32_t smrr_base;
+ uint32_t smrr_mask;
+};
+
+/*
+ * mmap_region_granularity must to return a size which is a positive non-zero
+ * integer multiple of the SMM size when SMM is in use. When not using SMM,
+ * this value should be set to 8 MiB.
+ */
+size_t mmap_region_granularity(void);
+
+/* Fills in the arguments for the entire SMM region covered by chipset
+ * protections. e.g. TSEG. */
+void smm_region(void **start, size_t *size);
+
+enum {
+ /* SMM handler area. */
+ SMM_SUBREGION_HANDLER,
+ /* SMM cache region. */
+ SMM_SUBREGION_CACHE,
+ /* Chipset specific area. */
+ SMM_SUBREGION_CHIPSET,
+ /* Total sub regions supported. */
+ SMM_SUBREGION_NUM,
+};
+
+/* Fills in the start and size for the requested SMM subregion. Returns
+ * 0 on susccess, < 0 on failure. */
+int smm_subregion(int sub, void **start, size_t *size);
+
+#if !defined(__PRE_RAM__) && !defined(__SMM___)
+#include <stdint.h>
+void southcluster_smm_clear_state(void);
+void southcluster_smm_enable_smi(void);
+void southcluster_smm_save_gpio_route(uint32_t route);
+#endif
+
+#endif /* _DENVERTON_NS_SMM_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/soc_util.h b/src/soc/intel/denverton_ns/include/soc/soc_util.h
new file mode 100644
index 0000000000..074ec16933
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/soc_util.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_SOC_UTIL_H_
+#define _DENVERTON_NS_SOC_UTIL_H_
+
+#ifndef __ACPI__
+#include <device/device.h>
+
+/* Silicon revisions */
+typedef enum {
+ SILICON_REV_DENVERTON_A0 = 0x00,
+ SILICON_REV_DENVERTON_A1 = 0x01,
+ SILICON_REV_DENVERTON_B0 = 0x02,
+} silicon_revision;
+
+/* soc_util.c */
+device_t get_hostbridge_dev(void);
+device_t get_lpc_dev(void);
+device_t get_pmc_dev(void);
+device_t get_smbus_dev(void);
+
+uint32_t get_pciebase(void);
+uint32_t get_pcielength(void);
+uint32_t get_tseg_memory(void);
+uint32_t get_top_of_low_memory(void);
+uint64_t get_top_of_upper_memory(void);
+uint16_t get_pmbase(void);
+uint16_t get_tcobase(void);
+
+/*
+* Secure functions.
+*/
+void *memcpy_s(void *dest, const void *src, size_t n);
+
+void mmio_andthenor32(void *addr, uint32_t val2and, uint32_t val2or);
+uint8_t silicon_stepping(void);
+
+/*
+* MMIO Read/Write
+*/
+#define MMIO8(x) (*((volatile u8 *)(x)))
+#define MMIO16(x) (*((volatile u16 *)(x)))
+#define MMIO32(x) (*((volatile u32 *)(x)))
+
+#define MMIO_AND_OR(bits, x, and, or) \
+ (MMIO##bits(x) = ((MMIO##bits(x) & (and)) | (or)))
+
+#define MMIO8_AND_OR(x, and, or) MMIO_AND_OR(8, x, and, or)
+#define MMIO16_AND_OR(x, and, or) MMIO_AND_OR(16, x, and, or)
+#define MMIO32_AND_OR(x, and, or) MMIO_AND_OR(32, x, and, or)
+#define MMIO32_OR(x, or) MMIO_AND_OR(32, x, ~0UL, or)
+#define MMIO32_AND(x, and) MMIO_AND_OR(32, x, and, 0UL)
+
+#endif //__ACPI__
+
+#endif /* _DENVERTON_NS_SOC_UTIL_H_ */
diff --git a/src/soc/intel/denverton_ns/include/soc/systemagent.h b/src/soc/intel/denverton_ns/include/soc/systemagent.h
new file mode 100644
index 0000000000..a02aea34d4
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/systemagent.h
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 - 2008 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_SYSTEMAGENT_H_
+#define _DENVERTON_NS_SYSTEMAGENT_H_
+
+#include <soc/iomap.h>
+
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+#define PCH_SA_DEV PCI_DEV(0, SA_DEV, SA_FUNC)
+
+#define MCHBAR 0x48 /* MCH space. */
+#define PCIEXBAR 0x60 /* PCI express space. */
+#define MASK_PCIEXBAR_256M 0xF0000000
+#define MASK_PCIEXBAR_128M 0xF8000000
+#define MASK_PCIEXBAR_64M 0xFC000000
+#define MASK_PCIEXBAR_LENGTH 0x6
+#define SHIFT_PCIEXBAR_LENGTH 0x1
+#define MASK_PCIEXBAR_LENGTH_256M (0x0 << SHIFT_PCIEXBAR_LENGTH)
+#define MASK_PCIEXBAR_LENGTH_128M (0x1 << SHIFT_PCIEXBAR_LENGTH)
+#define MASK_PCIEXBAR_LENGTH_64M (0x2 << SHIFT_PCIEXBAR_LENGTH)
+
+#define TOUUD_LO 0xa8 /* Top of Upper Usable DRAM - Low */
+#define MASK_TOUUD_LO 0xFFF00000
+#define TOUUD_HI 0xac /* Top of Upper Usable DRAM - High */
+#define MASK_TOUUD_HI 0x0000007F
+#define TOUUD TOUUD_LO /* Top of Upper Usable DRAM */
+#define MASK_TOUUD 0x7FFFF00000
+
+#define TSEGMB 0xb8 /* TSEG base */
+#define MASK_TSEGMB 0xFFF00000
+#define TOLUD 0xbc /* Top of Low Used Memory */
+#define MASK_TOLUD 0xFFF00000
+
+/* SideBand B-UNIT */
+#define B_UNIT 3
+
+/* SideBand C-UNIT */
+#define C_UNIT 8
+
+/* SideBand D-UNIT */
+#define D_UNIT 1
+
+/* SideBand P-UNIT */
+#define P_UNIT 4
+
+/*
+ * MCHBAR
+ */
+#define MCH_BASE_SIZE 0x8000
+#define MCH_BMISC 0x6800
+#define MCH_BMISC_SBVDRAM \
+ 0x08 /* Bit 3: 1 - reads targeting boot vector are routed to DRAM. */
+#define MCH_BMISC_ABSEGINDRAM \
+ 0x04 /* Bit 2: 1 - reads targeting A/B-segment are routed to DRAM. */
+#define MCH_BMISC_RFSDRAM \
+ 0x02 /* Bit 1: 1 - reads targeting E-segment are routed to DRAM. */
+#define MCH_BMISC_RESDRAM \
+ 0x01 /* Bit 0: 1 - reads targeting E-segment are routed to DRAM. */
+
+#define MCH_BAR_BIOS_RESET_CPL 0x7078
+#define RST_CPL_BIT (1 << 0)
+#define PCODE_INIT_DONE (1 << 8)
+#define MCH_BAR_CORE_EXISTS_MASK 0x7164
+#define MCH_BAR_CORE_DISABLE_MASK 0x7168
+
+/* Device 0:4.0 PCI configuration space (RAS) */
+
+/* Device 0:5.0 PCI configuration space (RCEC) */
+
+/* Top of 32bit usable memory */
+u32 top_of_32bit_ram(void);
+
+#endif //_DENVERTON_NS_SYSTEMAGENT_H_
diff --git a/src/soc/intel/denverton_ns/include/soc/uart.h b/src/soc/intel/denverton_ns/include/soc/uart.h
new file mode 100644
index 0000000000..29e9024d87
--- /dev/null
+++ b/src/soc/intel/denverton_ns/include/soc/uart.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DENVERTON_NS_UART_H
+#define _DENVERTON_NS_UART_H
+
+#define SIZE_OF_HSUART_RES 0x100
+#define HARCUVAR_UARTS_TO_INI 3
+#define PSR_OFFSET 0x30
+#define PCI_FUNC_RDCFG_HIDE 0x74
+
+#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2 * !!(condition)]))
+
+#endif /* _DENVERTON_NS_UART_H */