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Diffstat (limited to 'src/soc/intel/denverton_ns')
-rw-r--r--src/soc/intel/denverton_ns/romstage.c32
1 files changed, 10 insertions, 22 deletions
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 9c41486aa2..cbd451ae0d 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
#include <arch/romstage.h>
#include <arch/io.h>
#include <cbmem.h>
@@ -137,16 +136,8 @@ static void early_tco_init(void)
outw(reg16, tco_base + TCO2_STS);
}
-asmlinkage void car_stage_entry(void)
+void mainboard_romstage_entry(void)
{
-
- struct postcar_frame pcf;
- uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
-
- console_init();
-
printk(BIOS_DEBUG, "FSP TempRamInit was successful...\n");
mainboard_config_gpios();
@@ -158,9 +149,13 @@ asmlinkage void car_stage_entry(void)
#if CONFIG(DISPLAY_HOBS)
display_fsp_smbios_memory_info_hob();
#endif
+}
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ uintptr_t smm_base;
+ size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this point exact
@@ -168,12 +163,9 @@ asmlinkage void car_stage_entry(void)
* 16 megs under cbmem top which is a safe bet to cover ramstage.
*/
top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
MTRR_TYPE_WRBACK);
- /* Cache the memory-mapped boot media. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
-
/*
* Cache the TSEG region at the top of ram. This region is
* not restricted to SMM mode until SMM has been relocated.
@@ -181,12 +173,8 @@ asmlinkage void car_stage_entry(void)
* when relocating the SMM handler as well as using the TSEG
* region for other purposes.
*/
- if (CONFIG(HAVE_SMI_HANDLER)) {
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
- }
-
- run_postcar_phase(&pcf);
+ smm_region(&smm_base, &smm_size);
+ postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
}
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)