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Diffstat (limited to 'src/soc/intel/fsp_baytrail/Kconfig')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/Kconfig | 117 |
1 files changed, 0 insertions, 117 deletions
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig deleted file mode 100644 index 5a8bec995b..0000000000 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ /dev/null @@ -1,117 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOC_INTEL_FSP_BAYTRAIL - bool - help - Bay Trail I part support using the Intel FSP. - -if SOC_INTEL_FSP_BAYTRAIL - -config CPU_SPECIFIC_OPTIONS - def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select HAVE_SMI_HANDLER - select SOUTHBRIDGE_INTEL_COMMON_RESET - select NO_RELOCATABLE_RAMSTAGE - select PARALLEL_MP - select REG_SCRIPT - select SMP - select SPI_FLASH - select SSE2 - select TSC_SYNC_MFENCE - select UDELAY_TSC - select TSC_MONOTONIC_TIMER - select SUPPORT_CPU_UCODE_IN_CBFS - select MICROCODE_BLOB_NOT_HOOKED_UP - select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_SPI_CONSOLE_SUPPORT - select DRIVERS_I2C_DESIGNWARE - - # Microcode header files are delivered in FSP package - select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN - -config VBOOT - select VBOOT_STARTS_IN_ROMSTAGE - -config SOC_INTEL_FSP_BAYTRAIL_MD - bool - default n - -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/fsp_baytrail/bootblock/bootblock.c" - -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - -config MAX_CPUS - int - default 4 - -config CPU_ADDR_BITS - int - default 36 - -config SMM_TSEG_SIZE - hex - default 0x800000 - help - This is set by the FSP - -config SMM_RESERVED_SIZE - hex - default 0x100000 - -config VGA_BIOS_ID - string - default "8086,0f31" - help - This is the default PCI ID for the Bay Trail graphics - devices. This string names the vbios ROM in cbfs. - -config ENABLE_BUILTIN_COM1 - bool "Enable built-in legacy Serial Port" - help - The Baytrail SOC has one legacy serial port. Choose this option to - configure the pads and enable it. This serial port can be used for - the debug console. - -config VGA_BIOS_FILE - string - default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS - -config CPU_MICROCODE_HEADER_FILES - string - default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" - -config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ - int - default 133 - -config SOC_INTEL_I2C_DEV_MAX - int - default 7 - -## Baytrail Specific FSP Kconfig -source src/soc/intel/fsp_baytrail/fsp/Kconfig - -endif #SOC_INTEL_FSP_BAYTRAIL |