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-rw-r--r--src/soc/intel/fsp_baytrail/acpi/device_nvs.asl82
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/globalnvs.asl99
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/gpio.asl105
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/irq_helper.h124
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/irqlinks.asl487
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/irqroute.asl45
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/lpc.asl138
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/lpe.asl114
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/lpss.asl707
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/platform.asl32
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/scc.asl182
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/southcluster.asl294
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/usb.asl48
-rw-r--r--src/soc/intel/fsp_baytrail/acpi/xhci.asl31
14 files changed, 0 insertions, 2488 deletions
diff --git a/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl b/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl
deleted file mode 100644
index 54978cd2c0..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Device Enabled in ACPI Mode */
-
-S0EN, 8, // SDMA Enable
-S1EN, 8, // I2C1 Enable
-S2EN, 8, // I2C2 Enable
-S3EN, 8, // I2C3 Enable
-S4EN, 8, // I2C4 Enable
-S5EN, 8, // I2C5 Enable
-S6EN, 8, // I2C6 Enable
-S7EN, 8, // I2C7 Enable
-S8EN, 8, // SDMA2 Enable
-S9EN, 8, // SPI Enable
-SAEN, 8, // PWM1 Enable
-SBEN, 8, // PWM2 Enable
-SCEN, 8, // UART2 Enable
-SDEN, 8, // UART2 Enable
-C0EN, 8, // MMC Enable
-C1EN, 8, // SDIO Enable
-C2EN, 8, // SD Card Enable
-LPEN, 8, // LPE Enable
-
-/* BAR 0 */
-
-S0B0, 32, // SDMA BAR0
-S1B0, 32, // I2C1 BAR0
-S2B0, 32, // I2C2 BAR0
-S3B0, 32, // I2C3 BAR0
-S4B0, 32, // I2C4 BAR0
-S5B0, 32, // I2C5 BAR0
-S6B0, 32, // I2C6 BAR0
-S7B0, 32, // I2C7 BAR0
-S8B0, 32, // SDMA2 BAR0
-S9B0, 32, // SPI BAR0
-SAB0, 32, // PWM1 BAR0
-SBB0, 32, // PWM2 BAR0
-SCB0, 32, // UART1 BAR0
-SDB0, 32, // UART2 BAR0
-C0B0, 32, // MMC BAR0
-C1B0, 32, // SDIO BAR0
-C2B0, 32, // SD Card BAR0
-LPB0, 32, // LPE BAR0
-
-/* BAR 1 */
-
-S0B1, 32, // SDMA BAR1
-S1B1, 32, // I2C1 BAR1
-S2B1, 32, // I2C2 BAR1
-S3B1, 32, // I2C3 BAR1
-S4B1, 32, // I2C4 BAR1
-S5B1, 32, // I2C5 BAR1
-S6B1, 32, // I2C6 BAR1
-S7B1, 32, // I2C7 BAR1
-S8B1, 32, // SDMA2 BAR1
-S9B1, 32, // SPI BAR1
-SAB1, 32, // PWM1 BAR1
-SBB1, 32, // PWM2 BAR1
-SCB1, 32, // UART1 BAR1
-SDB1, 32, // UART2 BAR1
-C0B1, 32, // MMC BAR1
-C1B1, 32, // SDIO BAR1
-C2B1, 32, // SD Card BAR1
-LPB1, 32, // LPE BAR1
-
-/* Extra */
-
-LPFW, 32, // LPE BAR2 Firmware
diff --git a/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl b/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl
deleted file mode 100644
index c4d91a3c16..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Global Variables */
-
-Name(\PICM, 0) // IOAPIC/8259
-
-/* Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-
-External(NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
-Field (GNVS, ByteAcc, NoLock, Preserve)
-{
- /* Miscellaneous */
- Offset (0x00),
- OSYS, 16, // 0x00 - Operating System
- SMIF, 8, // 0x02 - SMI function
- PRM0, 8, // 0x03 - SMI function parameter
- PRM1, 8, // 0x04 - SMI function parameter
- SCIF, 8, // 0x05 - SCI function
- PRM2, 8, // 0x06 - SCI function parameter
- PRM3, 8, // 0x07 - SCI function parameter
- LCKF, 8, // 0x08 - Global Lock function for EC
- PRM4, 8, // 0x09 - Lock function parameter
- PRM5, 8, // 0x0a - Lock function parameter
- P80D, 32, // 0x0b - Debug port (IO 0x80) value
- LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
- PCNT, 8, // 0x11 - Processor count
- TPMP, 8, // 0x12 - TPM Present and Enabled
- TLVL, 8, // 0x13 - Throttle Level
- PPCM, 8, // 0x14 - Maximum P-state usable by OS
-
- /* Device Config */
- Offset (0x20),
- S5U0, 8, // 0x20 - Enable USB0 in S5
- S5U1, 8, // 0x21 - Enable USB1 in S5
- S3U0, 8, // 0x22 - Enable USB0 in S3
- S3U1, 8, // 0x23 - Enable USB1 in S3
- TACT, 8, // 0x24 - Thermal Active trip point
- TPSV, 8, // 0x25 - Thermal Passive trip point
- TCRT, 8, // 0x26 - Thermal Critical trip point
- DPTE, 8, // 0x27 - Enable DPTF
-
- /* Base addresses */
- Offset (0x30),
- CMEM, 32, // 0x30 - CBMEM TOC
- TOLM, 32, // 0x34 - Top of Low Memory
- CBMC, 32, // 0x38 - coreboot mem console pointer
-
- Offset (0x1000),
- #include <soc/intel/fsp_baytrail/acpi/device_nvs.asl>
-}
-
-/* Set flag to enable USB charging in S3 */
-Method (S3UE)
-{
- Store (One, \S3U0)
- Store (One, \S3U1)
-}
-
-/* Set flag to disable USB charging in S3 */
-Method (S3UD)
-{
- Store (Zero, \S3U0)
- Store (Zero, \S3U1)
-}
-
-/* Set flag to enable USB charging in S5 */
-Method (S5UE)
-{
- Store (One, \S5U0)
- Store (One, \S5U1)
-}
-
-/* Set flag to disable USB charging in S5 */
-Method (S5UD)
-{
- Store (Zero, \S5U0)
- Store (Zero, \S5U1)
-}
diff --git a/src/soc/intel/fsp_baytrail/acpi/gpio.asl b/src/soc/intel/fsp_baytrail/acpi/gpio.asl
deleted file mode 100644
index d0e9be5366..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/gpio.asl
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/intel/fsp_baytrail/include/soc/iomap.h>
-#include <soc/intel/fsp_baytrail/include/soc/irq.h>
-
-/* SouthCluster GPIO */
-Device (GPSC)
-{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
- Name (_UID, 1)
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
- {
- GPIO_SC_IRQ
- }
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- Return (0xF)
- }
-}
-
-/* NorthCluster GPIO */
-Device (GPNC)
-{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
- Name (_UID, 2)
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
- {
- GPIO_NC_IRQ
- }
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- Return (0xF)
- }
-}
-
-/* SUS GPIO */
-Device (GPSS)
-{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
- Name (_UID, 3)
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
- {
- GPIO_SUS_IRQ
- }
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- Return (0xF)
- }
-}
diff --git a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h
deleted file mode 100644
index 8d18aeaeb3..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronics Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-/*
- * This file intentionally gets included multiple times, to set pic and apic
- * modes, so should not have guard statements added.
- */
-
-/*
- * This file will use arch/x86/acpi/irqroute.asl and mainboard/irqroute.h
- * to generate the ACPI IRQ routing for the mainboard being compiled.
- * This method uses #defines in irqroute.h along with the macros contained
- * in this file to generate an IRQ routing for each PCI device in the system.
- */
-
-#undef PCI_DEV_PIRQ_ROUTES
-#undef ACPI_DEV_IRQ
-#undef PCI_DEV_PIRQ_ROUTE
-#undef PIRQ_PIC_ROUTES
-#undef PIRQ_PIC
-#undef IRQROUTE_H
-#undef ROOTPORT_METHODS
-#undef RP_METHOD
-#undef ROOTPORT_IRQ_ROUTES
-#undef RP_IRQ_ROUTES
-
-#if defined(PIC_MODE)
-
-#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
- Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
-
-#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
-Name(prefix_ ## func_ ## P, Package() \
-{ \
- ACPI_DEV_IRQ(0x0000, 0, a_), \
- ACPI_DEV_IRQ(0x0000, 1, b_), \
- ACPI_DEV_IRQ(0x0000, 2, c_), \
- ACPI_DEV_IRQ(0x0000, 3, d_), \
-})
-
-/* define as blank so ROOTPORT_METHODS only gets inserted once */
-#define ROOTPORT_METHODS(prefix_, dev_)
-
-#else /* defined(PIC_MODE) */
-
-#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
- Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
-
-#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
-Name(prefix_ ## func_ ## A, Package() \
-{ \
- ACPI_DEV_IRQ(0x0000, 0, a_), \
- ACPI_DEV_IRQ(0x0000, 1, b_), \
- ACPI_DEV_IRQ(0x0000, 2, c_), \
- ACPI_DEV_IRQ(0x0000, 3, d_), \
-})
-
-#define ROOTPORT_METHODS(prefix_, dev_) \
- RP_METHOD(prefix_, dev_, 0) \
- RP_METHOD(prefix_, dev_, 1) \
- RP_METHOD(prefix_, dev_, 2) \
- RP_METHOD(prefix_, dev_, 3) \
- RP_METHOD(prefix_, dev_, 4) \
- RP_METHOD(prefix_, dev_, 5) \
- RP_METHOD(prefix_, dev_, 6) \
- RP_METHOD(prefix_, dev_, 7)
-
-#endif /* defined(PIC_MODE) */
-
-#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
- ACPI_DEV_IRQ(dev_, 0, a_), \
- ACPI_DEV_IRQ(dev_, 1, b_), \
- ACPI_DEV_IRQ(dev_, 2, c_), \
- ACPI_DEV_IRQ(dev_, 3, d_)
-
-#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
- ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
- ROOTPORT_METHODS(prefix_, dev_)
-
-#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
- RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
- RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
- RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
- RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
- RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
- RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
- RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
- RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
-
-#define RP_METHOD(prefix_, dev_, func_)\
-Device(prefix_ ## 0 ## func_) \
-{ \
- Name(_ADR, dev_ ## 000 ## func_) \
- Name(_PRW, Package() { \
- 0, 0 \
- }) \
- Method(_PRT,0) { \
- If(PICM) { \
- Return (prefix_ ## func_ ## A) \
- } Else { \
- Return (prefix_ ## func_ ## P) \
- } \
- } \
-}
-
-/* Empty PIRQ_PIC definition. */
-#define PIRQ_PIC(pirq_, pic_irq_)
-
-/* Include the mainboard irq route definition */
-#include "irqroute.h"
diff --git a/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl b/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl
deleted file mode 100644
index 2d029242d8..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl
+++ /dev/null
@@ -1,487 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Device (LNKA)
-{
- Name (_HID, EISAID("PNP0C0F"))
- Name (_UID, 1)
-
- // Disable method
- Method (_DIS, 0, Serialized)
- {
- Store (0x80, PRTA)
- }
-
- // Possible Resource Settings for this Link
- Name (_PRS, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
- })
-
- // Current Resource Settings for this link
- Method (_CRS, 0, Serialized)
- {
- Name (RTLA, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared) {}
- })
- CreateWordField(RTLA, 1, IRQ0)
-
- // Clear the WordField
- Store (Zero, IRQ0)
-
- // Set the bit from PRTA
- ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
-
- Return (RTLA)
- }
-
- // Set Resource Setting for this IRQ link
- Method (_SRS, 1, Serialized)
- {
- CreateWordField(Arg0, 1, IRQ0)
-
- // Which bit is set?
- FindSetRightBit(IRQ0, Local0)
-
- Decrement(Local0)
- Store(Local0, PRTA)
- }
-
- // Status
- Method (_STA, 0, Serialized)
- {
- If(And(PRTA, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xb)
- }
- }
-}
-
-Device (LNKB)
-{
- Name (_HID, EISAID("PNP0C0F"))
- Name (_UID, 2)
-
- // Disable method
- Method (_DIS, 0, Serialized)
- {
- Store (0x80, PRTB)
- }
-
- // Possible Resource Settings for this Link
- Name (_PRS, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
- })
-
- // Current Resource Settings for this link
- Method (_CRS, 0, Serialized)
- {
- Name (RTLB, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared) {}
- })
- CreateWordField(RTLB, 1, IRQ0)
-
- // Clear the WordField
- Store (Zero, IRQ0)
-
- // Set the bit from PRTB
- ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
-
- Return (RTLB)
- }
-
- // Set Resource Setting for this IRQ link
- Method (_SRS, 1, Serialized)
- {
- CreateWordField(Arg0, 1, IRQ0)
-
- // Which bit is set?
- FindSetRightBit(IRQ0, Local0)
-
- Decrement(Local0)
- Store(Local0, PRTB)
- }
-
- // Status
- Method (_STA, 0, Serialized)
- {
- If(And(PRTB, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xb)
- }
- }
-}
-
-Device (LNKC)
-{
- Name (_HID, EISAID("PNP0C0F"))
- Name (_UID, 3)
-
- // Disable method
- Method (_DIS, 0, Serialized)
- {
- Store (0x80, PRTC)
- }
-
- // Possible Resource Settings for this Link
- Name (_PRS, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
- })
-
- // Current Resource Settings for this link
- Method (_CRS, 0, Serialized)
- {
- Name (RTLC, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared) {}
- })
- CreateWordField(RTLC, 1, IRQ0)
-
- // Clear the WordField
- Store (Zero, IRQ0)
-
- // Set the bit from PRTC
- ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
-
- Return (RTLC)
- }
-
- // Set Resource Setting for this IRQ link
- Method (_SRS, 1, Serialized)
- {
- CreateWordField(Arg0, 1, IRQ0)
-
- // Which bit is set?
- FindSetRightBit(IRQ0, Local0)
-
- Decrement(Local0)
- Store(Local0, PRTC)
- }
-
- // Status
- Method (_STA, 0, Serialized)
- {
- If(And(PRTC, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xb)
- }
- }
-}
-
-Device (LNKD)
-{
- Name (_HID, EISAID("PNP0C0F"))
- Name (_UID, 4)
-
- // Disable method
- Method (_DIS, 0, Serialized)
- {
- Store (0x80, PRTD)
- }
-
- // Possible Resource Settings for this Link
- Name (_PRS, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
- })
-
- // Current Resource Settings for this link
- Method (_CRS, 0, Serialized)
- {
- Name (RTLD, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared) {}
- })
- CreateWordField(RTLD, 1, IRQ0)
-
- // Clear the WordField
- Store (Zero, IRQ0)
-
- // Set the bit from PRTD
- ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
-
- Return (RTLD)
- }
-
- // Set Resource Setting for this IRQ link
- Method (_SRS, 1, Serialized)
- {
- CreateWordField(Arg0, 1, IRQ0)
-
- // Which bit is set?
- FindSetRightBit(IRQ0, Local0)
-
- Decrement(Local0)
- Store(Local0, PRTD)
- }
-
- // Status
- Method (_STA, 0, Serialized)
- {
- If(And(PRTD, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xb)
- }
- }
-}
-
-Device (LNKE)
-{
- Name (_HID, EISAID("PNP0C0F"))
- Name (_UID, 5)
-
- // Disable method
- Method (_DIS, 0, Serialized)
- {
- Store (0x80, PRTE)
- }
-
- // Possible Resource Settings for this Link
- Name (_PRS, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
- })
-
- // Current Resource Settings for this link
- Method (_CRS, 0, Serialized)
- {
- Name (RTLE, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared) {}
- })
- CreateWordField(RTLE, 1, IRQ0)
-
- // Clear the WordField
- Store (Zero, IRQ0)
-
- // Set the bit from PRTE
- ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
-
- Return (RTLE)
- }
-
- // Set Resource Setting for this IRQ link
- Method (_SRS, 1, Serialized)
- {
- CreateWordField(Arg0, 1, IRQ0)
-
- // Which bit is set?
- FindSetRightBit(IRQ0, Local0)
-
- Decrement(Local0)
- Store(Local0, PRTE)
- }
-
- // Status
- Method (_STA, 0, Serialized)
- {
- If(And(PRTE, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xb)
- }
- }
-}
-
-Device (LNKF)
-{
- Name (_HID, EISAID("PNP0C0F"))
- Name (_UID, 6)
-
- // Disable method
- Method (_DIS, 0, Serialized)
- {
- Store (0x80, PRTF)
- }
-
- // Possible Resource Settings for this Link
- Name (_PRS, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
- })
-
- // Current Resource Settings for this link
- Method (_CRS, 0, Serialized)
- {
- Name (RTLF, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared) {}
- })
- CreateWordField(RTLF, 1, IRQ0)
-
- // Clear the WordField
- Store (Zero, IRQ0)
-
- // Set the bit from PRTF
- ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
-
- Return (RTLF)
- }
-
- // Set Resource Setting for this IRQ link
- Method (_SRS, 1, Serialized)
- {
- CreateWordField(Arg0, 1, IRQ0)
-
- // Which bit is set?
- FindSetRightBit(IRQ0, Local0)
-
- Decrement(Local0)
- Store(Local0, PRTF)
- }
-
- // Status
- Method (_STA, 0, Serialized)
- {
- If(And(PRTF, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xb)
- }
- }
-}
-
-Device (LNKG)
-{
- Name (_HID, EISAID("PNP0C0F"))
- Name (_UID, 7)
-
- // Disable method
- Method (_DIS, 0, Serialized)
- {
- Store (0x80, PRTG)
- }
-
- // Possible Resource Settings for this Link
- Name (_PRS, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
- })
-
- // Current Resource Settings for this link
- Method (_CRS, 0, Serialized)
- {
- Name (RTLG, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared) {}
- })
- CreateWordField(RTLG, 1, IRQ0)
-
- // Clear the WordField
- Store (Zero, IRQ0)
-
- // Set the bit from PRTG
- ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
-
- Return (RTLG)
- }
-
- // Set Resource Setting for this IRQ link
- Method (_SRS, 1, Serialized)
- {
- CreateWordField(Arg0, 1, IRQ0)
-
- // Which bit is set?
- FindSetRightBit(IRQ0, Local0)
-
- Decrement(Local0)
- Store(Local0, PRTG)
- }
-
- // Status
- Method (_STA, 0, Serialized)
- {
- If(And(PRTG, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xb)
- }
- }
-}
-
-Device (LNKH)
-{
- Name (_HID, EISAID("PNP0C0F"))
- Name (_UID, 8)
-
- // Disable method
- Method (_DIS, 0, Serialized)
- {
- Store (0x80, PRTH)
- }
-
- // Possible Resource Settings for this Link
- Name (_PRS, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
- })
-
- // Current Resource Settings for this link
- Method (_CRS, 0, Serialized)
- {
- Name (RTLH, ResourceTemplate()
- {
- IRQ(Level, ActiveLow, Shared) {}
- })
- CreateWordField(RTLH, 1, IRQ0)
-
- // Clear the WordField
- Store (Zero, IRQ0)
-
- // Set the bit from PRTH
- ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
-
- Return (RTLH)
- }
-
- // Set Resource Setting for this IRQ link
- Method (_SRS, 1, Serialized)
- {
- CreateWordField(Arg0, 1, IRQ0)
-
- // Which bit is set?
- FindSetRightBit(IRQ0, Local0)
-
- Decrement(Local0)
- Store(Local0, PRTH)
- }
-
- // Status
- Method (_STA, 0, Serialized)
- {
- If(And(PRTH, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xb)
- }
- }
-}
diff --git a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl
deleted file mode 100644
index 4f3a744ff5..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- /*
- * PICM comes from _PIC, which returns the following:
- * 0 - PIC mode
- * 1 - APIC mode
- * 2 - SAPIC mode
- */
- If (PICM) {
- Return (Package() {
- #undef PIC_MODE
- #include "irq_helper.h"
- PCI_DEV_PIRQ_ROUTES
- })
- } Else {
- Return (Package() {
- #define PIC_MODE
- #include "irq_helper.h"
- PCI_DEV_PIRQ_ROUTES
- })
- }
-
-}
-
-PCIE_BRIDGE_IRQ_ROUTES
-#undef PIC_MODE
-#include "irq_helper.h"
-PCIE_BRIDGE_IRQ_ROUTES
diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl
deleted file mode 100644
index 7cdf1aa5d0..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// Intel LPC Bus Device - 0:1f.0
-
-Device (LPCB)
-{
- Name(_ADR, 0x001f0000)
-
- #include "irqlinks.asl"
-
- #include "acpi/ec.asl"
-
- Device (DMAC) // DMA Controller
- {
- Name(_HID, EISAID("PNP0200"))
- Name(_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x00, 0x00, 0x01, 0x20)
- IO (Decode16, 0x81, 0x81, 0x01, 0x11)
- IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
- IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
- DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
- })
- }
-
- Device (FWH) // Firmware Hub
- {
- Name (_HID, EISAID("INT0800"))
- Name (_CRS, ResourceTemplate()
- {
- Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
- })
- }
-
- Device (HPET)
- {
- Name (_HID, EISAID("PNP0103"))
- Name (_CID, 0x010CD041)
-
- Method (_STA, 0) // Device Status
- {
- Return (0xf) // Enable and show device
- }
-
- Name(_CRS, ResourceTemplate()
- {
- Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400)
- })
- }
-
- Device(PIC) // 8259 Interrupt Controller
- {
- Name(_HID,EISAID("PNP0000"))
- Name(_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x20, 0x20, 0x01, 0x02)
- IO (Decode16, 0x24, 0x24, 0x01, 0x02)
- IO (Decode16, 0x28, 0x28, 0x01, 0x02)
- IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
- IO (Decode16, 0x30, 0x30, 0x01, 0x02)
- IO (Decode16, 0x34, 0x34, 0x01, 0x02)
- IO (Decode16, 0x38, 0x38, 0x01, 0x02)
- IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
- IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
- IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
- IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
- IO (Decode16, 0xac, 0xac, 0x01, 0x02)
- IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
- IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
- IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
- IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
- IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
- IRQNoFlags () { 2 }
- })
- }
-
- Device(LDRC) // LPC device: Resource consumption
- {
- Name (_HID, EISAID("PNP0C02"))
- Name (_UID, 2)
-
- Name (RBUF, ResourceTemplate()
- {
- IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
- IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
- IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- Return (RBUF)
- }
- }
-
- Device (RTC) // Real Time Clock
- {
- Name (_HID, EISAID("PNP0B00"))
- Name (_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x70, 0x70, 1, 8)
-// Disable as Windows doesn't like it, and systems don't seem to use it.
-// IRQNoFlags() { 8 }
- })
- }
-
- Device (TIMR) // Intel 8254 timer
- {
- Name(_HID, EISAID("PNP0100"))
- Name(_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x40, 0x40, 0x01, 0x04)
- IO (Decode16, 0x50, 0x50, 0x10, 0x04)
- IRQNoFlags() {0}
- })
- }
-
- // Include mainboard's superio.asl file.
- #include "acpi/superio.asl"
-}
diff --git a/src/soc/intel/fsp_baytrail/acpi/lpe.asl b/src/soc/intel/fsp_baytrail/acpi/lpe.asl
deleted file mode 100644
index d1dbd3a4b2..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/lpe.asl
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Device (LPEA)
-{
- Name (_HID, "80860F28")
- Name (_CID, "80860F28")
- Name (_UID, 1)
- Name (_DDN, "Low Power Audio Controller")
- Name (_PR0, Package () { PLPE })
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0)
- Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1)
- Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPE_DMA0_IRQ
- }
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPE_DMA1_IRQ
- }
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPE_SSP0_IRQ
- }
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPE_SSP1_IRQ
- }
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPE_SSP2_IRQ
- }
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPE_IPC2HOST_IRQ
- }
- })
-
- Method (_CRS)
- {
- /* Update BAR0 from NVS */
- CreateDwordField (^RBUF, ^BAR0._BAS, BAS0)
- Store (\LPB0, BAS0)
-
- /* Update BAR1 from NVS */
- CreateDwordField (^RBUF, ^BAR1._BAS, BAS1)
- Store (\LPB1, BAS1)
-
- /* Update LPE FW from NVS */
- CreateDwordField (^RBUF, ^BAR2._BAS, BAS2)
- Store (\LPFW, BAS2)
-
- /* Append any Mainboard defined GPIOs */
- If (CondRefOf (^GBUF, Local0)) {
- ConcatenateResTemplate (^RBUF, Local0, Local1)
- Return (Local1)
- }
-
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\LPEN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, LPB1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- PowerResource (PLPE, 0, 0)
- {
- Method (_STA)
- {
- Return (1)
- }
-
- Method (_OFF)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_ON)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
- }
-}
diff --git a/src/soc/intel/fsp_baytrail/acpi/lpss.asl b/src/soc/intel/fsp_baytrail/acpi/lpss.asl
deleted file mode 100644
index 6cac06a13e..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/lpss.asl
+++ /dev/null
@@ -1,707 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Device (SDM1)
-{
- Name (_HID, "INTL9C60")
- Name (_UID, 1)
- Name (_DDN, "DMA Controller #1")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_DMA1_IRQ
- }
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\S0B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S0EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-}
-
-Device (SDM2)
-{
- Name (_HID, "INTL9C60")
- Name (_UID, 2)
- Name (_DDN, "DMA Controller #2")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_DMA2_IRQ
- }
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\S8B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S8EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-}
-
-Device (I2C1)
-{
- Name (_HID, "80860F41")
- Name (_UID, 1)
- Name (_DDN, "I2C Controller #1")
-
- /* Standard Mode: HCNT, LCNT, SDA Hold Time */
- Name (SSCN, Package () { 0x200, 0x200, 0x6 })
-
- /* Fast Mode: HCNT, LCNT, SDA Hold Time */
- Name (FMCN, Package () { 0x55, 0x99, 0x6 })
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_I2C1_IRQ
- }
- FixedDMA (0x10, 0x0, Width32Bit, )
- FixedDMA (0x11, 0x1, Width32Bit, )
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\S1B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S1EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, S1B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
-
-Device (I2C2)
-{
- Name (_HID, "80860F41")
- Name (_UID, 2)
- Name (_DDN, "I2C Controller #2")
-
- /* Standard Mode: HCNT, LCNT, SDA Hold Time */
- Name (SSCN, Package () { 0x200, 0x200, 0x6 })
-
- /* Fast Mode: HCNT, LCNT, SDA Hold Time */
- Name (FMCN, Package () { 0x55, 0x99, 0x6 })
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_I2C2_IRQ
- }
- FixedDMA (0x10, 0x0, Width32Bit, )
- FixedDMA (0x11, 0x1, Width32Bit, )
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\S2B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S2EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, S2B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
-
-Device (I2C3)
-{
- Name (_HID, "80860F41")
- Name (_UID, 3)
- Name (_DDN, "I2C Controller #3")
-
- /* Standard Mode: HCNT, LCNT, SDA Hold Time */
- Name (SSCN, Package () { 0x200, 0x200, 0x6 })
-
- /* Fast Mode: HCNT, LCNT, SDA Hold Time */
- Name (FMCN, Package () { 0x55, 0x99, 0x6 })
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_I2C3_IRQ
- }
- FixedDMA (0x10, 0x0, Width32Bit, )
- FixedDMA (0x11, 0x1, Width32Bit, )
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\S3B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S3EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, S3B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
-
-Device (I2C4)
-{
- Name (_HID, "80860F41")
- Name (_UID, 4)
- Name (_DDN, "I2C Controller #4")
-
- /* Standard Mode: HCNT, LCNT, SDA Hold Time */
- Name (SSCN, Package () { 0x200, 0x200, 0x6 })
-
- /* Fast Mode: HCNT, LCNT, SDA Hold Time */
- Name (FMCN, Package () { 0x55, 0x99, 0x6 })
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_I2C4_IRQ
- }
- FixedDMA (0x10, 0x0, Width32Bit, )
- FixedDMA (0x11, 0x1, Width32Bit, )
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\S4B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S4EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, S4B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
-
-Device (I2C5)
-{
- Name (_HID, "80860F41")
- Name (_UID, 5)
- Name (_DDN, "I2C Controller #5")
-
- /* Standard Mode: HCNT, LCNT, SDA Hold Time */
- Name (SSCN, Package () { 0x200, 0x200, 0x6 })
-
- /* Fast Mode: HCNT, LCNT, SDA Hold Time */
- Name (FMCN, Package () { 0x55, 0x99, 0x6 })
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_I2C5_IRQ
- }
- FixedDMA (0x10, 0x0, Width32Bit, )
- FixedDMA (0x11, 0x1, Width32Bit, )
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\S5B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S5EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, S5B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
-
-Device (I2C6)
-{
- Name (_HID, "80860F41")
- Name (_UID, 6)
- Name (_DDN, "I2C Controller #6")
-
- /* Standard Mode: HCNT, LCNT, SDA Hold Time */
- Name (SSCN, Package () { 0x200, 0x200, 0x6 })
-
- /* Fast Mode: HCNT, LCNT, SDA Hold Time */
- Name (FMCN, Package () { 0x55, 0x99, 0x6 })
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_I2C6_IRQ
- }
- FixedDMA (0x10, 0x0, Width32Bit, )
- FixedDMA (0x11, 0x1, Width32Bit, )
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\S6B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S6EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, S6B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
-
-Device (I2C7)
-{
- Name (_HID, "80860F41")
- Name (_UID, 7)
- Name (_DDN, "I2C Controller #7")
-
- /* Standard Mode: HCNT, LCNT, SDA Hold Time */
- Name (SSCN, Package () { 0x200, 0x200, 0x6 })
-
- /* Fast Mode: HCNT, LCNT, SDA Hold Time */
- Name (FMCN, Package () { 0x55, 0x99, 0x6 })
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_I2C7_IRQ
- }
- FixedDMA (0x10, 0x0, Width32Bit, )
- FixedDMA (0x11, 0x1, Width32Bit, )
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\S7B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S7EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, S7B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
-
-Device (SPI1)
-{
- Name (_HID, "80860F0E")
- Name (_UID, 1)
- Name (_DDN, "SPI Controller #2")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_SPI_IRQ
- }
- FixedDMA (0x0, 0x0, Width32Bit, )
- FixedDMA (0x1, 0x1, Width32Bit, )
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\S9B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S9EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, S9B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
-
-Device (PWM1)
-{
- Name (_HID, "80860F09")
- Name (_UID, 1)
- Name (_DDN, "PWM Controller #1")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\SAB0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\SAEN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-}
-
-Device (PWM2)
-{
- Name (_HID, "80860F09")
- Name (_UID, 2)
- Name (_DDN, "PWM Controller #2")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\SBB0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\SBEN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-}
-
-Device (UAR1)
-{
- Name (_HID, "80860F0A")
- Name (_UID, 1)
- Name (_DDN, "HS-UART Controller #1")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_HSUART1_IRQ
- }
- FixedDMA (0x2, 0x2, Width32Bit, )
- FixedDMA (0x3, 0x3, Width32Bit, )
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\SCB0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\SCEN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, SCB1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
-
-Device (UAR2)
-{
- Name (_HID, "80860F0A")
- Name (_UID, 2)
- Name (_DDN, "HS-UART Controller #2")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_HSUART2_IRQ
- }
- FixedDMA (0x4, 0x4, Width32Bit, )
- FixedDMA (0x5, 0x5, Width32Bit, )
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\SDB0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\SDEN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, SDB1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
diff --git a/src/soc/intel/fsp_baytrail/acpi/platform.asl b/src/soc/intel/fsp_baytrail/acpi/platform.asl
deleted file mode 100644
index 01be3514fd..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/platform.asl
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/intel/common/acpi/platform.asl>
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
- Return(Package(){0,0})
-}
diff --git a/src/soc/intel/fsp_baytrail/acpi/scc.asl b/src/soc/intel/fsp_baytrail/acpi/scc.asl
deleted file mode 100644
index c26511c751..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/scc.asl
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Device (EMMC)
-{
- Name (_HID, "80860F14")
- Name (_CID, "PNP0D40")
- Name (_UID, 1)
- Name (_DDN, "eMMC Controller 4.5")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- SCC_EMMC_IRQ
- }
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\C0B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\C0EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, C0B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Device (EM45)
- {
- /* Slot 0, Function 8 */
- Name (_ADR, 0x8)
-
- Method (_RMV, 0, NotSerialized)
- {
- Return (0)
- }
- }
-}
-
-Device (SDIO)
-{
- Name (_HID, "INT33BB")
- Name (_CID, "PNP0D40")
- Name (_UID, 2)
- Name (_DDN, "SDIO Controller")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- SCC_SDIO_IRQ
- }
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\C1B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\C1EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, C1B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
-
-Device (SDCD)
-{
- Name (_HID, "80860F16")
- Name (_CID, "PNP0D40")
- Name (_UID, 3)
- Name (_DDN, "SD Card Controller")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- SCC_SD_IRQ
- }
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\C2B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\C2EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, C2B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl
deleted file mode 100644
index ef4523b004..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/intel/fsp_baytrail/include/soc/iomap.h>
-#include <soc/intel/fsp_baytrail/include/soc/irq.h>
-#include "../include/soc/baytrail.h"
-
-Scope(\)
-{
- // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
-
- OperationRegion(IO_T, SystemIO, 0x800, 0x10)
- Field(IO_T, ByteAcc, NoLock, Preserve)
- {
- Offset(0x8),
- TRP0, 8 // IO-Trap at 0x808
- }
-
- // Intel Legacy Block
- OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
- Field (ILBS, AnyAcc, NoLock, Preserve)
- {
- Offset (0x8),
- PRTA, 8,
- PRTB, 8,
- PRTC, 8,
- PRTD, 8,
- PRTE, 8,
- PRTF, 8,
- PRTG, 8,
- PRTH, 8,
- }
-}
-
-Name(_HID,EISAID("PNP0A08")) // PCIe
-Name(_CID,EISAID("PNP0A03")) // PCI
-
-Name(_BBN, 0)
-
-Name (MCRS, ResourceTemplate()
-{
- // Bus Numbers
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
-
- // IO Region 0
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
-
- // PCI Config Space
- Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
-
- // IO Region 1
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
-
- // VGA memory (0xa0000-0xbffff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
- 0x00020000,,, ASEG)
-
- // OPROM reserved (0xc0000-0xc3fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
- 0x00004000,,, OPR0)
-
- // OPROM reserved (0xc4000-0xc7fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
- 0x00004000,,, OPR1)
-
- // OPROM reserved (0xc8000-0xcbfff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
- 0x00004000,,, OPR2)
-
- // OPROM reserved (0xcc000-0xcffff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
- 0x00004000,,, OPR3)
-
- // OPROM reserved (0xd0000-0xd3fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
- 0x00004000,,, OPR4)
-
- // OPROM reserved (0xd4000-0xd7fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
- 0x00004000,,, OPR5)
-
- // OPROM reserved (0xd8000-0xdbfff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
- 0x00004000,,, OPR6)
-
- // OPROM reserved (0xdc000-0xdffff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
- 0x00004000,,, OPR7)
-
- // BIOS Extension (0xe0000-0xe3fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
- 0x00004000,,, ESG0)
-
- // BIOS Extension (0xe4000-0xe7fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
- 0x00004000,,, ESG1)
-
- // BIOS Extension (0xe8000-0xebfff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
- 0x00004000,,, ESG2)
-
- // BIOS Extension (0xec000-0xeffff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
- 0x00004000,,, ESG3)
-
- // System BIOS (0xf0000-0xfffff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
- 0x00010000,,, FSEG)
-
- // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000,,, PMEM)
-
- // TPM Area (0xfed40000-0xfed44fff)
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
- 0x00005000,,, TPMR)
-
- // High PCI Memory Region
- QwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000,,, UMEM)
-})
-
-Method (_CRS, 0, Serialized)
-{
- // Update PCI resource area
- CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
- CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
- CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
-
- // TOLM is BMBOUND accessible from IOSF so is saved in NVS
- Store (\TOLM, PMIN)
- Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
- Add (Subtract (PMAX, PMIN), 1, PLEN)
-
- // Update High PCI resource area
- CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
- CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
- CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
-
- Store(0x40000000 * 48, UMIN) // Set base address to 48GB
- Store(0x40000000 * 16, ULEN) // Allocate 16GB for PCI space
- Add(UMIN, Subtract(ULEN, 1), UMAX)
-
- Return (MCRS)
-}
-
-/* Device Resource Consumption */
-Device (PDRC)
-{
- Name (_HID, EISAID("PNP0C02"))
- Name (_UID, 1)
-
- Name (PDRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
- Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
- Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
- Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
- Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
- Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
- Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
- Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
- })
-
- // Current Resource Settings
- Method (_CRS, 0, Serialized)
- {
- Return(PDRS)
- }
-}
-
-Method (_OSC, 4)
-{
- /* Check for proper GUID */
- If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
- {
- /* Let OS control everything */
- Return (Arg3)
- }
- Else
- {
- /* Unrecognized UUID */
- CreateDWordField (Arg3, 0, CDW1)
- Or (CDW1, 4, CDW1)
- Return (Arg3)
- }
-}
-
-/* IOSF MBI Interface for kernel access */
-Device (IOSF)
-{
- Name (_HID, "INT33BD")
- Name (_CID, "INT33BD")
- Name (_UID, 1)
-
- Name (RBUF, ResourceTemplate ()
- {
- /* MCR / MDR / MCRX */
- Memory32Fixed (ReadWrite, 0, 12, RBAR)
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
- Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS)
- Return (^RBUF)
- }
-}
-
-// LPC Bridge 0:1f.0
-#include "lpc.asl"
-
-#if INCLUDE_EHCI
-// USB EHCI 0:1d.0
-#include "usb.asl"
-#endif
-
-#if INCLUDE_XHCI
-// USB XHCI 0:14.0
-#include "xhci.asl"
-#endif
-
-// IRQ routing for each PCI device
-#include "irqroute.asl"
-
-Scope (\_SB)
-{
- // GPIO Devices
- #include "gpio.asl"
-
-#if INCLUDE_LPSS
- // LPSS Devices
- #include "lpss.asl"
-#endif
-
-#if INCLUDE_SCC
- // SCC Devices
- #include "scc.asl"
-#endif
-
-#if INCLUDE_LPE
- // LPE Device
- #include "lpe.asl"
-#endif
-}
diff --git a/src/soc/intel/fsp_baytrail/acpi/usb.asl b/src/soc/intel/fsp_baytrail/acpi/usb.asl
deleted file mode 100644
index c60bfcec46..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/usb.asl
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Intel Baytrail USB support */
-
-// EHCI Controller 0:1d.0
-
-Device (EHC1)
-{
- Name(_ADR, 0x001d0000)
-
- Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
-
- // Leave USB ports on for to allow Wake from USB
-
- Method(_S3D,0) // Highest D State in S3 State
- {
- Return (2)
- }
-
- Method(_S4D,0) // Highest D State in S4 State
- {
- Return (2)
- }
-
- Device (HUB7)
- {
- Name (_ADR, 0x00000000)
-
- Device (PRT1) { Name (_ADR, 1) } // USB Port 0
- Device (PRT2) { Name (_ADR, 2) } // USB Port 1
- Device (PRT3) { Name (_ADR, 3) } // USB Port 2
- Device (PRT4) { Name (_ADR, 4) } // USB Port 3
- }
-}
diff --git a/src/soc/intel/fsp_baytrail/acpi/xhci.asl b/src/soc/intel/fsp_baytrail/acpi/xhci.asl
deleted file mode 100644
index dbd34474f8..0000000000
--- a/src/soc/intel/fsp_baytrail/acpi/xhci.asl
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Device (XHCI)
-{
- Name (_ADR, 0x00140000)
- Name (_PRW, Package () { 0x0d, 3 })
- Name (_S3D, 3) /* Highest D state in S3 state */
-
- Device (RHUB)
- {
- Name (_ADR, 0x00000000)
- Device (PRT1) { Name (_ADR, 1) }
- Device (PRT2) { Name (_ADR, 2) }
- Device (PRT3) { Name (_ADR, 3) }
- Device (PRT4) { Name (_ADR, 4) }
- }
-}