diff options
Diffstat (limited to 'src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index f11b206ed4..48f0cdd755 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -31,12 +31,6 @@ #include <soc/iomap.h> #include <soc/smm.h> -#ifdef __PRE_RAM__ -#include <soc/romstage.h> -#endif - -#ifdef __PRE_RAM__ - /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) { @@ -307,10 +301,9 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; -#if CONFIG(ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); -#endif + if (CONFIG(ENABLE_MRC_CACHE)) + pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); if (prev_sleep_state == ACPI_S3) { /* S3 resume */ @@ -335,5 +328,3 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, return; } - -#endif /* __PRE_RAM__ */ |