summaryrefslogtreecommitdiff
path: root/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/fsp_baytrail/include/soc/baytrail.h')
-rw-r--r--src/soc/intel/fsp_baytrail/include/soc/baytrail.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
index 34831b13bb..3a2fcaa635 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
@@ -35,23 +35,24 @@
#else
#define DEFAULT_RCBA 0xfed1c000
#endif
-/* Everything below this line is ignored in the DSDT */
-#ifndef __ACPI__
/* Device 0:0.0 PCI configuration space (Host Bridge) */
+#define SKPAD 0xFC
/* SOC types */
#define SOC_TYPE_BAYTRAIL 0x0F1C
+/* Everything below this line is ignored in the DSDT */
+#ifndef __ACPI__
#ifndef __ASSEMBLER__
-static inline void barrier(void) { asm("" ::: "memory"); }
+#include <device/device.h>
-#define SKPAD 0xFC
+static inline void barrier(void) { asm("" ::: "memory"); }
int bridge_silicon_revision(void);
void rangeley_early_initialization(void);
+void set_max_freq(void);
-#ifndef __PRE_RAM__
/* soc.c */
int soc_silicon_revision(void);
int soc_silicon_type(void);
@@ -60,8 +61,7 @@ void soc_enable(struct device *dev);
void report_platform_info(void);
-#endif /* __PRE_RAM__ */
#endif /* __ASSEMBLER__ */
-
#endif /* __ACPI__ */
+
#endif