diff options
Diffstat (limited to 'src/soc/intel/fsp_baytrail/include')
-rw-r--r-- | src/soc/intel/fsp_baytrail/include/soc/baytrail.h | 14 | ||||
-rw-r--r-- | src/soc/intel/fsp_baytrail/include/soc/pmc.h | 2 | ||||
-rw-r--r-- | src/soc/intel/fsp_baytrail/include/soc/ramstage.h | 1 | ||||
-rw-r--r-- | src/soc/intel/fsp_baytrail/include/soc/romstage.h | 13 |
4 files changed, 9 insertions, 21 deletions
diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 34831b13bb..3a2fcaa635 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -35,23 +35,24 @@ #else #define DEFAULT_RCBA 0xfed1c000 #endif -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ /* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define SKPAD 0xFC /* SOC types */ #define SOC_TYPE_BAYTRAIL 0x0F1C +/* Everything below this line is ignored in the DSDT */ +#ifndef __ACPI__ #ifndef __ASSEMBLER__ -static inline void barrier(void) { asm("" ::: "memory"); } +#include <device/device.h> -#define SKPAD 0xFC +static inline void barrier(void) { asm("" ::: "memory"); } int bridge_silicon_revision(void); void rangeley_early_initialization(void); +void set_max_freq(void); -#ifndef __PRE_RAM__ /* soc.c */ int soc_silicon_revision(void); int soc_silicon_type(void); @@ -60,8 +61,7 @@ void soc_enable(struct device *dev); void report_platform_info(void); -#endif /* __PRE_RAM__ */ #endif /* __ASSEMBLER__ */ - #endif /* __ACPI__ */ + #endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index 75daba540e..71c8e10446 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -283,6 +283,8 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +uint32_t chipset_prev_sleep_state(uint32_t clear); + #if CONFIG(ELOG) void southcluster_log_state(void); #else diff --git a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h index e8f81bb5c0..45fda9e937 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h @@ -22,7 +22,6 @@ * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); void baytrail_init_cpus(struct device *dev); -void set_max_freq(void); void southcluster_enable_dev(struct device *dev); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index 5f0bd8d9c3..dce953993a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -17,31 +17,18 @@ #ifndef _BAYTRAIL_ROMSTAGE_H_ #define _BAYTRAIL_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - -void report_platform_info(void); - #include <stdint.h> #include <drivers/intel/fsp1_0/fsp_util.h> void main(FSP_INFO_HEADER *fsp_info_header); -uint32_t chipset_prev_sleep_state(uint32_t clear); #define NUM_ROMSTAGE_TS 4 void tco_disable(void); void punit_init(void); -void set_max_freq(void); void early_mainboard_romstage_entry(void); void late_mainboard_romstage_entry(void); void get_func_disables(uint32_t *mask, uint32_t *mask2); - -#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif #endif /* _BAYTRAIL_ROMSTAGE_H_ */ |