diff options
Diffstat (limited to 'src/soc/intel/fsp_baytrail')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/cpu.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/include/soc/msr.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index a69d046e7b..89ea4c2ada 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -35,7 +35,7 @@ /* Core level MSRs */ static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), + REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), REG_MSR_OR(MSR_POWER_MISC, 0x44), diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index ea1d790867..4435256be8 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -19,7 +19,7 @@ #define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 |