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-rw-r--r--src/soc/intel/icelake/include/soc/me.h43
1 files changed, 43 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/include/soc/me.h b/src/soc/intel/icelake/include/soc/me.h
new file mode 100644
index 0000000000..b1646a2716
--- /dev/null
+++ b/src/soc/intel/icelake/include/soc/me.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ICELAKE_ME_H_
+#define _ICELAKE_ME_H_
+
+/* ME Host Firmware Status register 1 */
+union me_hfsts1 {
+ u32 data;
+ struct {
+ u32 working_state: 4;
+ u32 mfg_mode: 1;
+ u32 fpt_bad: 1;
+ u32 operation_state: 3;
+ u32 fw_init_complete: 1;
+ u32 ft_bup_ld_flr: 1;
+ u32 update_in_progress: 1;
+ u32 error_code: 4;
+ u32 operation_mode: 4;
+ u32 reset_count: 4;
+ u32 boot_options_present: 1;
+ u32 reserved1: 1;
+ u32 bist_test_state: 1;
+ u32 bist_reset_request: 1;
+ u32 current_power_source: 2;
+ u32 reserved: 1;
+ u32 d0i3_support_valid: 1;
+ } __packed fields;
+};
+
+#endif /* _ICELAKE_ME_H_ */