diff options
Diffstat (limited to 'src/soc/intel/icelake')
| -rw-r--r-- | src/soc/intel/icelake/acpi/gpio.asl | 39 | ||||
| -rw-r--r-- | src/soc/intel/icelake/gpio.c | 95 | ||||
| -rw-r--r-- | src/soc/intel/icelake/include/soc/gpio.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/icelake/include/soc/gpio_defs.h | 411 | ||||
| -rw-r--r-- | src/soc/intel/icelake/include/soc/gpio_soc_defs.h | 539 | ||||
| -rw-r--r-- | src/soc/intel/icelake/include/soc/pcr_ids.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/icelake/include/soc/pmc.h | 16 |
7 files changed, 527 insertions, 576 deletions
diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl index 5784fb150e..c8d4fefdbd 100644 --- a/src/soc/intel/icelake/acpi/gpio.asl +++ b/src/soc/intel/icelake/acpi/gpio.asl @@ -19,7 +19,7 @@ Device (GPIO) { - Name (_HID, "INT34BB") + Name (_HID, "INT3455") Name (_UID, 0) Name (_DDN, "GPIO Controller") @@ -28,8 +28,8 @@ Device (GPIO) Memory32Fixed (ReadWrite, 0, 0, COM0) Memory32Fixed (ReadWrite, 0, 0, COM1) Memory32Fixed (ReadWrite, 0, 0, COM2) - Memory32Fixed (ReadWrite, 0, 0, COM3) Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) { GPIO_IRQ14 } }) @@ -54,19 +54,18 @@ Device (GPIO) Store (^^PCRB (PID_GPIOCOM2), BAS2) Store (GPIO_BASE_SIZE, LEN2) - /* GPIO Community 3 */ - CreateDWordField (^RBUF, ^COM3._BAS, BAS3) - CreateDWordField (^RBUF, ^COM3._LEN, LEN3) - Store (^^PCRB (PID_GPIOCOM3), BAS3) - Store (GPIO_BASE_SIZE, LEN3) - - /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4) Store (^^PCRB (PID_GPIOCOM4), BAS4) Store (GPIO_BASE_SIZE, LEN4) + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + Store (^^PCRB (PID_GPIOCOM5), BAS5) + Store (GPIO_BASE_SIZE, LEN5) + Return (RBUF) } @@ -83,13 +82,13 @@ Device (GPIO) Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11))) + If (LAnd (LGreaterEqual (Arg0, GPP_G0), LLessEqual (Arg0, GPP_A23))) { Store (PID_GPIOCOM0, Local0) Subtract (Arg0, GPP_A0, Local1) } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_52))) + If (LAnd (LGreaterEqual (Arg0, GPP_H0), LLessEqual (Arg0, GPP_F19))) { Store (PID_GPIOCOM1, Local0) Subtract (Arg0, GPP_D0, Local1) @@ -97,21 +96,21 @@ Method (GADD, 1, NotSerialized) /* GPIO Community 2 */ If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11))) { - Store (PID_GPIOCOM1, Local0) + Store (PID_GPIOCOM2, Local0) Subtract (Arg0, GPD0, Local1) } - /* GPIO Community 3 */ - If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_78))) - { - Store (PID_GPIOCOM1, Local0) - Subtract (Arg0, HDA_BCLK, Local1) - } - /* GPIO Community 04*/ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_67))) + /* GPIO Community 4 */ + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_E23))) { Store (PID_GPIOCOM4, Local0) Subtract (Arg0, GPP_C0, Local1) } + /* GPIO Community 05*/ + If (LAnd (LGreaterEqual (Arg0, GPP_R0), LLessEqual (Arg0, GPP_S7))) + { + Store (PID_GPIOCOM5, Local0) + Subtract (Arg0, GPP_R0, Local1) + } Store (PCRB (Local0), Local2) Add (Local2, PAD_CFG_BASE, Local2) Return (Add (Local2, Multiply (Local1, 16))) diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c index e965494274..b244437503 100644 --- a/src/soc/intel/icelake/gpio.c +++ b/src/soc/intel/icelake/gpio.c @@ -33,63 +33,63 @@ static const struct reset_mapping rst_map_com0[] = { }; static const struct pad_group icl_community0_groups[] = { - INTEL_GPP(GPP_A0, GPP_A0, GPIO_RSVD_0), /* GPP_A */ - INTEL_GPP(GPP_A0, GPP_B0, GPIO_RSVD_2), /* GPP_B */ - INTEL_GPP(GPP_A0, GPP_G0, GPP_G7), /* GPP_G */ - INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */ + INTEL_GPP(GPP_G0, GPP_G0, GPP_G7), /* GPP_G */ + INTEL_GPP(GPP_G0, GPP_B0, GPP_B23), /* GPP_B */ + INTEL_GPP(GPP_G0, GPIO_RSVD_0, GPIO_RSVD_1), + INTEL_GPP(GPP_G0, GPP_A0, GPP_A23), /* GPP_A */ }; static const struct pad_group icl_community1_groups[] = { - INTEL_GPP(GPP_D0, GPP_D0, GPIO_RSVD_12), /* GPP_D */ - INTEL_GPP(GPP_D0, GPP_F0, GPP_F23), /* GPP_F */ - INTEL_GPP(GPP_D0, GPP_H0, GPP_H23), /* GPP_H */ - INTEL_GPP(GPP_D0, GPIO_RSVD_12, GPIO_RSVD_52), /* VGPIO */ + INTEL_GPP(GPP_H0, GPP_H0, GPP_H23), /* GPP_H */ + INTEL_GPP(GPP_H0, GPP_D0, GPIO_RSVD_2), /* GPP_D */ + INTEL_GPP(GPP_H0, GPP_F0, GPP_F19), /* GPP_F */ }; static const struct pad_group icl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ + INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ }; -static const struct pad_group icl_community3_groups[] = { - INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */ - INTEL_GPP(HDA_BCLK, GPIO_RSVD_68, GPIO_RSVD_78), /* CPU */ -}; static const struct pad_group icl_community4_groups[] = { - INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */ - INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP_E */ - INTEL_GPP(GPP_C0, GPIO_RSVD_53, GPIO_RSVD_61), /* JTAG */ - INTEL_GPP(GPP_C0, GPIO_RSVD_62, GPIO_RSVD_67), /* HVMOS */ + INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */ + INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP_E */ + INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_8), +}; + + +static const struct pad_group icl_community5_groups[] = { + INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */ + INTEL_GPP(GPP_C0, GPP_S0, GPP_S7), /* GPP_S */ }; static const struct pad_community icl_communities[] = { - { /* GPP A, B, G, SPI */ + { /* GPP G, B, A */ .port = PID_GPIOCOM0, - .first_pad = GPP_A0, - .last_pad = GPIO_RSVD_11, + .first_pad = GPP_G0, + .last_pad = GPP_A23, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_ABG", + .name = "GPP_GBA", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map_com0, .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = icl_community0_groups, .num_groups = ARRAY_SIZE(icl_community0_groups), - }, { /* GPP D, F, H, VGPIO */ + }, { /* GPP H, D, F */ .port = PID_GPIOCOM1, - .first_pad = GPP_D0, - .last_pad = GPIO_RSVD_52, + .first_pad = GPP_H0, + .last_pad = GPP_F19, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_DFH", + .name = "GPP_HDF", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), @@ -111,38 +111,38 @@ static const struct pad_community icl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = icl_community2_groups, .num_groups = ARRAY_SIZE(icl_community2_groups), - }, { /* AZA, CPU */ - .port = PID_GPIOCOM3, - .first_pad = HDA_BCLK, - .last_pad = GPIO_RSVD_78, - .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, + }, { /* GPP C, E */ + .port = PID_GPIOCOM4, + .first_pad = GPP_C0, + .last_pad = GPP_E23, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GP_AC", + .name = "GPP_CE", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = icl_community3_groups, - .num_groups = ARRAY_SIZE(icl_community3_groups), - }, { /* GPP C, E, JTAG, HVMOS */ - .port = PID_GPIOCOM4, - .first_pad = GPP_C0, - .last_pad = GPIO_RSVD_67, - .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .groups = icl_community4_groups, + .num_groups = ARRAY_SIZE(icl_community4_groups), + }, { /* GPP R, S */ + .port = PID_GPIOCOM5, + .first_pad = GPP_R0, + .last_pad = GPP_S7, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, - .name = "GPP_CEJ", + .name = "GPP_RS", .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), - .groups = icl_community4_groups, - .num_groups = ARRAY_SIZE(icl_community4_groups), + .groups = icl_community5_groups, + .num_groups = ARRAY_SIZE(icl_community5_groups), } }; @@ -155,15 +155,18 @@ const struct pad_community *soc_gpio_get_community(size_t *num_communities) const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) { static const struct pmc_to_gpio_route routes[] = { - { PMC_GPP_A, GPP_A }, + { PMC_GPP_G, GPP_G }, { PMC_GPP_B, GPP_B }, - { PMC_GPP_C, GPP_C }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_H, GPP_H }, { PMC_GPP_D, GPP_D }, - { PMC_GPP_E, GPP_E }, { PMC_GPP_F, GPP_F }, - { PMC_GPP_G, GPP_G }, - { PMC_GPP_H, GPP_H }, { PMC_GPD, GPD }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_E, GPP_E }, + { PMC_GPP_R, GPP_R }, + { PMC_GPP_S, GPP_S } + }; *num = ARRAY_SIZE(routes); return routes; diff --git a/src/soc/intel/icelake/include/soc/gpio.h b/src/soc/intel/icelake/include/soc/gpio.h index 2e55e74b51..333dba1a15 100644 --- a/src/soc/intel/icelake/include/soc/gpio.h +++ b/src/soc/intel/icelake/include/soc/gpio.h @@ -19,6 +19,6 @@ #include <soc/gpio_defs.h> #include <intelblocks/gpio.h> -#define CROS_GPIO_DEVICE_NAME "INT34BB:00" +#define CROS_GPIO_DEVICE_NAME "INT3455:00" #endif diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index 44425f4b2e..86d5fb2671 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -30,216 +30,235 @@ #define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) -#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) #define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) #define NUM_GPI_STATUS_REGS \ ((NUM_GPIO_COM0_GPI_REGS) +\ (NUM_GPIO_COM1_GPI_REGS) +\ (NUM_GPIO_COM2_GPI_REGS) +\ - (NUM_GPIO_COM3_GPI_REGS) +\ - (NUM_GPIO_COM4_GPI_REGS)) + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) /* * IOxAPIC IRQs for the GPIOs */ -/* Group A */ -#define GPP_A0_IRQ 0x18 -#define GPP_A1_IRQ 0x19 -#define GPP_A2_IRQ 0x1a -#define GPP_A3_IRQ 0x1b -#define GPP_A4_IRQ 0x1c -#define GPP_A5_IRQ 0x1d -#define GPP_A6_IRQ 0x1e -#define GPP_A7_IRQ 0x1f -#define GPP_A8_IRQ 0x20 -#define GPP_A9_IRQ 0x21 -#define GPP_A10_IRQ 0x22 -#define GPP_A11_IRQ 0x23 -#define GPP_A12_IRQ 0x24 -#define GPP_A13_IRQ 0x25 -#define GPP_A14_IRQ 0x26 -#define GPP_A15_IRQ 0x27 -#define GPP_A16_IRQ 0x28 -#define GPP_A17_IRQ 0x29 -#define GPP_A18_IRQ 0x2a -#define GPP_A19_IRQ 0x2b -#define GPP_A20_IRQ 0x2c -#define GPP_A21_IRQ 0x2d -#define GPP_A22_IRQ 0x2e -#define GPP_A23_IRQ 0x2f +/* Group G */ +#define GPP_G0_IRQ 0x18 +#define GPP_G1_IRQ 0x19 +#define GPP_G2_IRQ 0x1a +#define GPP_G3_IRQ 0x1b +#define GPP_G4_IRQ 0x1c +#define GPP_G5_IRQ 0x1d +#define GPP_G6_IRQ 0x1e +#define GPP_G7_IRQ 0x1f + /* Group B */ -#define GPP_B0_IRQ 0x30 -#define GPP_B1_IRQ 0x31 -#define GPP_B2_IRQ 0x32 -#define GPP_B3_IRQ 0x33 -#define GPP_B4_IRQ 0x34 -#define GPP_B5_IRQ 0x35 -#define GPP_B6_IRQ 0x36 -#define GPP_B7_IRQ 0x37 -#define GPP_B8_IRQ 0x38 -#define GPP_B9_IRQ 0x39 -#define GPP_B10_IRQ 0x3a -#define GPP_B11_IRQ 0x3b -#define GPP_B12_IRQ 0x3c -#define GPP_B13_IRQ 0x3d -#define GPP_B14_IRQ 0x3e -#define GPP_B15_IRQ 0x3f -#define GPP_B16_IRQ 0x40 -#define GPP_B17_IRQ 0x41 -#define GPP_B18_IRQ 0x42 -#define GPP_B19_IRQ 0x43 -#define GPP_B20_IRQ 0x44 -#define GPP_B21_IRQ 0x45 -#define GPP_B22_IRQ 0x46 -#define GPP_B23_IRQ 0x47 -/* Group C */ -#define GPP_C0_IRQ 0x48 -#define GPP_C1_IRQ 0x49 -#define GPP_C2_IRQ 0x4a -#define GPP_C3_IRQ 0x4b -#define GPP_C4_IRQ 0x4c -#define GPP_C5_IRQ 0x4d -#define GPP_C6_IRQ 0x4e -#define GPP_C7_IRQ 0x4f -#define GPP_C8_IRQ 0x50 -#define GPP_C9_IRQ 0x51 -#define GPP_C10_IRQ 0x52 -#define GPP_C11_IRQ 0x53 -#define GPP_C12_IRQ 0x54 -#define GPP_C13_IRQ 0x55 -#define GPP_C14_IRQ 0x56 -#define GPP_C15_IRQ 0x57 -#define GPP_C16_IRQ 0x58 -#define GPP_C17_IRQ 0x59 -#define GPP_C18_IRQ 0x5a -#define GPP_C19_IRQ 0x5b -#define GPP_C20_IRQ 0x5c -#define GPP_C21_IRQ 0x5d -#define GPP_C22_IRQ 0x5e -#define GPP_C23_IRQ 0x5f +#define GPP_B0_IRQ 0x20 +#define GPP_B1_IRQ 0x21 +#define GPP_B2_IRQ 0x22 +#define GPP_B3_IRQ 0x23 +#define GPP_B4_IRQ 0x24 +#define GPP_B5_IRQ 0x25 +#define GPP_B6_IRQ 0x26 +#define GPP_B7_IRQ 0x27 +#define GPP_B8_IRQ 0x28 +#define GPP_B9_IRQ 0x29 +#define GPP_B10_IRQ 0x2a +#define GPP_B11_IRQ 0x2b +#define GPP_B12_IRQ 0x2c +#define GPP_B13_IRQ 0x2d +#define GPP_B14_IRQ 0x2e +#define GPP_B15_IRQ 0x2f +#define GPP_B16_IRQ 0x30 +#define GPP_B17_IRQ 0x31 +#define GPP_B18_IRQ 0x32 +#define GPP_B19_IRQ 0x33 +#define GPP_B20_IRQ 0x34 +#define GPP_B21_IRQ 0x35 +#define GPP_B22_IRQ 0x36 +#define GPP_B23_IRQ 0x37 + +/* Group A */ +#define GPP_A0_IRQ 0x38 +#define GPP_A1_IRQ 0x39 +#define GPP_A2_IRQ 0x3a +#define GPP_A3_IRQ 0x3b +#define GPP_A4_IRQ 0x3c +#define GPP_A5_IRQ 0x3d +#define GPP_A6_IRQ 0x3e +#define GPP_A7_IRQ 0x3f +#define GPP_A8_IRQ 0x40 +#define GPP_A9_IRQ 0x41 +#define GPP_A10_IRQ 0x42 +#define GPP_A11_IRQ 0x43 +#define GPP_A12_IRQ 0x44 +#define GPP_A13_IRQ 0x45 +#define GPP_A14_IRQ 0x46 +#define GPP_A15_IRQ 0x47 +#define GPP_A16_IRQ 0x48 +#define GPP_A17_IRQ 0x49 +#define GPP_A18_IRQ 0x4a +#define GPP_A19_IRQ 0x4b +#define GPP_A20_IRQ 0x4c +#define GPP_A21_IRQ 0x4d +#define GPP_A22_IRQ 0x4e +#define GPP_A23_IRQ 0x4f + +/* Group H */ +#define GPP_H0_IRQ 0x70 +#define GPP_H1_IRQ 0x71 +#define GPP_H2_IRQ 0x72 +#define GPP_H3_IRQ 0x73 +#define GPP_H4_IRQ 0x74 +#define GPP_H5_IRQ 0x75 +#define GPP_H6_IRQ 0x76 +#define GPP_H7_IRQ 0x77 +#define GPP_H8_IRQ 0x18 +#define GPP_H9_IRQ 0x19 +#define GPP_H10_IRQ 0x1a +#define GPP_H11_IRQ 0x1b +#define GPP_H12_IRQ 0x1c +#define GPP_H13_IRQ 0x1d +#define GPP_H14_IRQ 0x1e +#define GPP_H15_IRQ 0x1f +#define GPP_H16_IRQ 0x20 +#define GPP_H17_IRQ 0x21 +#define GPP_H18_IRQ 0x22 +#define GPP_H19_IRQ 0x23 +#define GPP_H20_IRQ 0x24 +#define GPP_H21_IRQ 0x25 +#define GPP_H22_IRQ 0x26 +#define GPP_H23_IRQ 0x27 + /* Group D */ -#define GPP_D0_IRQ 0x60 -#define GPP_D1_IRQ 0x61 -#define GPP_D2_IRQ 0x62 -#define GPP_D3_IRQ 0x63 -#define GPP_D4_IRQ 0x64 -#define GPP_D5_IRQ 0x65 -#define GPP_D6_IRQ 0x66 -#define GPP_D7_IRQ 0x67 -#define GPP_D8_IRQ 0x68 -#define GPP_D9_IRQ 0x69 -#define GPP_D10_IRQ 0x6a -#define GPP_D11_IRQ 0x6b -#define GPP_D12_IRQ 0x6c -#define GPP_D13_IRQ 0x6d -#define GPP_D14_IRQ 0x6e -#define GPP_D15_IRQ 0x6f -#define GPP_D16_IRQ 0x70 -#define GPP_D17_IRQ 0x71 -#define GPP_D18_IRQ 0x72 -#define GPP_D19_IRQ 0x73 -#define GPP_D20_IRQ 0x74 -#define GPP_D21_IRQ 0x75 -#define GPP_D22_IRQ 0x76 -#define GPP_D23_IRQ 0x77 -/* Group E */ -#define GPP_E0_IRQ 0x18 -#define GPP_E1_IRQ 0x19 -#define GPP_E2_IRQ 0x1a -#define GPP_E3_IRQ 0x1b -#define GPP_E4_IRQ 0x1c -#define GPP_E5_IRQ 0x1d -#define GPP_E6_IRQ 0x1e -#define GPP_E7_IRQ 0x1f -#define GPP_E8_IRQ 0x20 -#define GPP_E9_IRQ 0x21 -#define GPP_E10_IRQ 0x22 -#define GPP_E11_IRQ 0x23 -#define GPP_E12_IRQ 0x24 -#define GPP_E13_IRQ 0x25 -#define GPP_E14_IRQ 0x26 -#define GPP_E15_IRQ 0x27 -#define GPP_E16_IRQ 0x28 -#define GPP_E17_IRQ 0x29 -#define GPP_E18_IRQ 0x2a -#define GPP_E19_IRQ 0x2b -#define GPP_E20_IRQ 0x2c -#define GPP_E21_IRQ 0x2d -#define GPP_E22_IRQ 0x2e -#define GPP_E23_IRQ 0x2f +#define GPP_D0_IRQ 0x28 +#define GPP_D1_IRQ 0x29 +#define GPP_D2_IRQ 0x2a +#define GPP_D3_IRQ 0x2b +#define GPP_D4_IRQ 0x2c +#define GPP_D5_IRQ 0x2d +#define GPP_D6_IRQ 0x2e +#define GPP_D7_IRQ 0x2f +#define GPP_D8_IRQ 0x30 +#define GPP_D9_IRQ 0x31 +#define GPP_D10_IRQ 0x32 +#define GPP_D11_IRQ 0x33 +#define GPP_D12_IRQ 0x34 +#define GPP_D13_IRQ 0x35 +#define GPP_D14_IRQ 0x36 +#define GPP_D15_IRQ 0x37 +#define GPP_D16_IRQ 0x38 +#define GPP_D17_IRQ 0x39 +#define GPP_D18_IRQ 0x3a +#define GPP_D19_IRQ 0x3b + /* Group F */ -#define GPP_F0_IRQ 0x30 -#define GPP_F1_IRQ 0x31 -#define GPP_F2_IRQ 0x32 -#define GPP_F3_IRQ 0x33 -#define GPP_F4_IRQ 0x34 -#define GPP_F5_IRQ 0x35 -#define GPP_F6_IRQ 0x36 -#define GPP_F7_IRQ 0x37 -#define GPP_F8_IRQ 0x38 -#define GPP_F9_IRQ 0x39 -#define GPP_F10_IRQ 0x3a -#define GPP_F11_IRQ 0x3b -#define GPP_F12_IRQ 0x3c -#define GPP_F13_IRQ 0x3d -#define GPP_F14_IRQ 0x3e -#define GPP_F15_IRQ 0x3f -#define GPP_F16_IRQ 0x40 -#define GPP_F17_IRQ 0x41 -#define GPP_F18_IRQ 0x42 -#define GPP_F19_IRQ 0x43 -#define GPP_F20_IRQ 0x44 -#define GPP_F21_IRQ 0x45 -#define GPP_F22_IRQ 0x46 -#define GPP_F23_IRQ 0x47 -/* Group G */ -#define GPP_G0_IRQ 0x6c -#define GPP_G1_IRQ 0x6d -#define GPP_G2_IRQ 0x6e -#define GPP_G3_IRQ 0x6f -#define GPP_G4_IRQ 0x70 -#define GPP_G5_IRQ 0x71 -#define GPP_G6_IRQ 0x72 -#define GPP_G7_IRQ 0x73 +#define GPP_F0_IRQ 0x40 +#define GPP_F1_IRQ 0x41 +#define GPP_F2_IRQ 0x42 +#define GPP_F3_IRQ 0x43 +#define GPP_F4_IRQ 0x44 +#define GPP_F5_IRQ 0x45 +#define GPP_F6_IRQ 0x46 +#define GPP_F7_IRQ 0x47 +#define GPP_F8_IRQ 0x48 +#define GPP_F9_IRQ 0x49 +#define GPP_F10_IRQ 0x4a +#define GPP_F11_IRQ 0x4b +#define GPP_F12_IRQ 0x4c +#define GPP_F13_IRQ 0x4d +#define GPP_F14_IRQ 0x4e +#define GPP_F15_IRQ 0x4f +#define GPP_F16_IRQ 0x50 +#define GPP_F17_IRQ 0x51 +#define GPP_F18_IRQ 0x52 +#define GPP_F19_IRQ 0x53 + /* Group GPD */ -#define GPD0_IRQ 0x60 -#define GPD1_IRQ 0x61 -#define GPD2_IRQ 0x62 -#define GPD3_IRQ 0x63 -#define GPD4_IRQ 0x64 -#define GPD5_IRQ 0x65 -#define GPD6_IRQ 0x66 -#define GPD7_IRQ 0x67 -#define GPD8_IRQ 0x68 -#define GPD9_IRQ 0x69 -#define GPD10_IRQ 0x6a -#define GPD11_IRQ 0x6b -/* Group H */ -#define GPP_H0_IRQ 0x48 -#define GPP_H1_IRQ 0x49 -#define GPP_H2_IRQ 0x4a -#define GPP_H3_IRQ 0x4b -#define GPP_H4_IRQ 0x4c -#define GPP_H5_IRQ 0x4d -#define GPP_H6_IRQ 0x4e -#define GPP_H7_IRQ 0x4f -#define GPP_H8_IRQ 0x50 -#define GPP_H9_IRQ 0x51 -#define GPP_H10_IRQ 0x52 -#define GPP_H11_IRQ 0x53 -#define GPP_H12_IRQ 0x54 -#define GPP_H13_IRQ 0x55 -#define GPP_H14_IRQ 0x56 -#define GPP_H15_IRQ 0x57 -#define GPP_H16_IRQ 0x58 -#define GPP_H17_IRQ 0x59 -#define GPP_H18_IRQ 0x5a -#define GPP_H19_IRQ 0x5b -#define GPP_H20_IRQ 0x5c -#define GPP_H21_IRQ 0x5d -#define GPP_H22_IRQ 0x5e -#define GPP_H23_IRQ 0x5f +#define GPD0_IRQ 0x64 +#define GPD1_IRQ 0x65 +#define GPD2_IRQ 0x66 +#define GPD3_IRQ 0x67 +#define GPD4_IRQ 0x68 +#define GPD5_IRQ 0x69 +#define GPD6_IRQ 0x6a +#define GPD7_IRQ 0x6b +#define GPD8_IRQ 0x6c +#define GPD9_IRQ 0x6d +#define GPD10_IRQ 0x6e +#define GPD11_IRQ 0x6f + +/* Group C */ +#define GPP_C0_IRQ 0x5a +#define GPP_C1_IRQ 0x5b +#define GPP_C2_IRQ 0x5c +#define GPP_C3_IRQ 0x5d +#define GPP_C4_IRQ 0x5e +#define GPP_C5_IRQ 0x5f +#define GPP_C6_IRQ 0x60 +#define GPP_C7_IRQ 0x61 +#define GPP_C8_IRQ 0x62 +#define GPP_C9_IRQ 0x63 +#define GPP_C10_IRQ 0x64 +#define GPP_C11_IRQ 0x65 +#define GPP_C12_IRQ 0x66 +#define GPP_C13_IRQ 0x67 +#define GPP_C14_IRQ 0x68 +#define GPP_C15_IRQ 0x69 +#define GPP_C16_IRQ 0x6a +#define GPP_C17_IRQ 0x6b +#define GPP_C18_IRQ 0x6c +#define GPP_C19_IRQ 0x6d +#define GPP_C20_IRQ 0x6e +#define GPP_C21_IRQ 0x6f +#define GPP_C22_IRQ 0x70 +#define GPP_C23_IRQ 0x71 +/* Group E */ +#define GPP_E0_IRQ 0x72 +#define GPP_E1_IRQ 0x73 +#define GPP_E2_IRQ 0x74 +#define GPP_E3_IRQ 0x75 +#define GPP_E4_IRQ 0x76 +#define GPP_E5_IRQ 0x77 +#define GPP_E6_IRQ 0x18 +#define GPP_E7_IRQ 0x19 +#define GPP_E8_IRQ 0x1a +#define GPP_E9_IRQ 0x1b +#define GPP_E10_IRQ 0x1c +#define GPP_E11_IRQ 0x1d +#define GPP_E12_IRQ 0x1e +#define GPP_E13_IRQ 0x1f +#define GPP_E14_IRQ 0x20 +#define GPP_E15_IRQ 0x21 +#define GPP_E16_IRQ 0x22 +#define GPP_E17_IRQ 0x23 +#define GPP_E18_IRQ 0x24 +#define GPP_E19_IRQ 0x25 +#define GPP_E20_IRQ 0x26 +#define GPP_E21_IRQ 0x27 +#define GPP_E22_IRQ 0x28 +#define GPP_E23_IRQ 0x29 + +/* Group R*/ +#define GPP_R0_IRQ 0x50 +#define GPP_R1_IRQ 0x51 +#define GPP_R2_IRQ 0x52 +#define GPP_R3_IRQ 0x53 +#define GPP_R4_IRQ 0x54 +#define GPP_R5_IRQ 0x55 +#define GPP_R6_IRQ 0x56 +#define GPP_R7_IRQ 0x57 + +/* Group S */ +#define GPP_S0_IRQ 0x5c +#define GPP_S1_IRQ 0x5d +#define GPP_S2_IRQ 0x5e +#define GPP_S3_IRQ 0x5f +#define GPP_S4_IRQ 0x60 +#define GPP_S5_IRQ 0x61 +#define GPP_S6_IRQ 0x62 +#define GPP_S7_IRQ 0x63 /* Register defines. */ #define GPIO_MISCCFG 0x10 diff --git a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h index 34216bc307..e3eaf62d5c 100644 --- a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h @@ -21,334 +21,263 @@ * The GPIO groups are accessed through register blocks called * communities. */ -#define GPP_A 0 +#define GPP_G 0 #define GPP_B 1 -#define GPP_G 2 -#define GROUP_SPI 3 +#define GPP_A 2 +#define GPP_H 3 #define GPP_D 4 #define GPP_F 5 -#define GPP_H 6 -#define GROUP_VGPIO 7 -#define GPD 9 -#define GROUP_AZA 0xA -#define GROUP_CPU 0xB -#define GPP_C 0xC -#define GPP_E 0xD -#define GROUP_JTAG 0xE -#define GROUP_HVMOS 0xF +#define GPD 6 +#define GPP_C 7 +#define GPP_E 8 +#define GPP_R 9 +#define GPP_S 0xA -#define GPIO_NUM_GROUPS 15 +#define GPIO_NUM_GROUPS 11 #define GPIO_MAX_NUM_PER_GROUP 24 /* * GPIOs are ordered monotonically increasing to match ACPI/OS driver. */ -/* Group A */ -#define GPP_A0 0 -#define GPP_A1 1 -#define GPP_A2 2 -#define GPP_A3 3 -#define GPP_A4 4 -#define GPP_A5 5 -#define GPP_A6 6 -#define GPP_A7 7 -#define GPP_A8 8 -#define GPP_A9 9 -#define GPP_A10 10 -#define GPP_A11 11 -#define GPP_A12 12 -#define GPP_A13 13 -#define GPP_A14 14 -#define GPP_A15 15 -#define GPP_A16 16 -#define GPP_A17 17 -#define GPP_A18 18 -#define GPP_A19 19 -#define GPP_A20 20 -#define GPP_A21 21 -#define GPP_A22 22 -#define GPP_A23 23 -#define GPIO_RSVD_0 24 -/* Group B */ -#define GPP_B0 25 -#define GPP_B1 26 -#define GPP_B2 27 -#define GPP_B3 28 -#define GPP_B4 29 -#define GPP_B5 30 -#define GPP_B6 31 -#define GPP_B7 32 -#define GPP_B8 33 -#define GPP_B9 34 -#define GPP_B10 35 -#define GPP_B11 36 -#define GPP_B12 37 -#define GPP_B13 38 -#define GPP_B14 39 -#define GPP_B15 40 -#define GPP_B16 41 -#define GPP_B17 42 -#define GPP_B18 43 -#define GPP_B19 44 -#define GPP_B20 45 -#define GPP_B21 46 -#define GPP_B22 47 -#define GPP_B23 48 -#define GPIO_RSVD_1 49 -#define GPIO_RSVD_2 50 /* Group G */ -#define GPP_G0 51 -#define GPP_G1 52 -#define GPP_G2 53 -#define GPP_G3 54 -#define GPP_G4 55 -#define GPP_G5 56 -#define GPP_G6 57 -#define GPP_G7 58 -/* Group SPI */ -#define GPIO_RSVD_3 59 -#define GPIO_RSVD_4 60 -#define GPIO_RSVD_5 61 -#define GPIO_RSVD_6 62 -#define GPIO_RSVD_7 63 -#define GPIO_RSVD_8 64 -#define GPIO_RSVD_9 65 -#define GPIO_RSVD_10 66 -#define GPIO_RSVD_11 67 +#define GPP_G0 0 +#define GPP_G1 1 +#define GPP_G2 2 +#define GPP_G3 3 +#define GPP_G4 4 +#define GPP_G5 5 +#define GPP_G6 6 +#define GPP_G7 7 -#define NUM_GPIO_COM0_PADS (GPIO_RSVD_11 - GPP_A0 + 1) +/* Group B */ +#define GPP_B0 8 +#define GPP_B1 9 +#define GPP_B2 10 +#define GPP_B3 11 +#define GPP_B4 12 +#define GPP_B5 13 +#define GPP_B6 14 +#define GPP_B7 15 +#define GPP_B8 16 +#define GPP_B9 17 +#define GPP_B10 18 +#define GPP_B11 19 +#define GPP_B12 20 +#define GPP_B13 21 +#define GPP_B14 22 +#define GPP_B15 23 +#define GPP_B16 24 +#define GPP_B17 25 +#define GPP_B18 26 +#define GPP_B19 27 +#define GPP_B20 28 +#define GPP_B21 29 +#define GPP_B22 30 +#define GPP_B23 31 +#define GPIO_RSVD_0 32 +#define GPIO_RSVD_1 33 + +/* Group A */ +#define GPP_A0 34 +#define GPP_A1 35 +#define GPP_A2 36 +#define GPP_A3 37 +#define GPP_A4 38 +#define GPP_A5 39 +#define GPP_A6 40 +#define GPP_A7 41 +#define GPP_A8 42 +#define GPP_A9 43 +#define GPP_A10 44 +#define GPP_A11 45 +#define GPP_A12 46 +#define GPP_A13 47 +#define GPP_A14 48 +#define GPP_A15 49 +#define GPP_A16 50 +#define GPP_A17 51 +#define GPP_A18 52 +#define GPP_A19 53 +#define GPP_A20 54 +#define GPP_A21 55 +#define GPP_A22 56 +#define GPP_A23 57 + +#define NUM_GPIO_COM0_PADS (GPP_A23 - GPP_G0 + 1) -/* Group D */ -#define GPP_D0 68 -#define GPP_D1 69 -#define GPP_D2 70 -#define GPP_D3 71 -#define GPP_D4 72 -#define GPP_D5 73 -#define GPP_D6 74 -#define GPP_D7 75 -#define GPP_D8 76 -#define GPP_D9 77 -#define GPP_D10 78 -#define GPP_D11 79 -#define GPP_D12 80 -#define GPP_D13 81 -#define GPP_D14 82 -#define GPP_D15 83 -#define GPP_D16 84 -#define GPP_D17 85 -#define GPP_D18 86 -#define GPP_D19 87 -#define GPP_D20 88 -#define GPP_D21 89 -#define GPP_D22 90 -#define GPP_D23 91 -#define GPIO_RSVD_12 92 -/* Group F */ -#define GPP_F0 93 -#define GPP_F1 94 -#define GPP_F2 95 -#define GPP_F3 96 -#define GPP_F4 97 -#define GPP_F5 98 -#define GPP_F6 99 -#define GPP_F7 100 -#define GPP_F8 101 -#define GPP_F9 102 -#define GPP_F10 103 -#define GPP_F11 104 -#define GPP_F12 105 -#define GPP_F13 106 -#define GPP_F14 107 -#define GPP_F15 108 -#define GPP_F16 109 -#define GPP_F17 110 -#define GPP_F18 111 -#define GPP_F19 112 -#define GPP_F20 113 -#define GPP_F21 114 -#define GPP_F22 115 -#define GPP_F23 116 /* Group H */ -#define GPP_H0 117 -#define GPP_H1 118 -#define GPP_H2 119 -#define GPP_H3 120 -#define GPP_H4 121 -#define GPP_H5 122 -#define GPP_H6 123 -#define GPP_H7 124 -#define GPP_H8 125 -#define GPP_H9 126 -#define GPP_H10 127 -#define GPP_H11 128 -#define GPP_H12 129 -#define GPP_H13 130 -#define GPP_H14 131 -#define GPP_H15 132 -#define GPP_H16 133 -#define GPP_H17 134 -#define GPP_H18 135 -#define GPP_H19 136 -#define GPP_H20 137 -#define GPP_H21 138 -#define GPP_H22 139 -#define GPP_H23 140 -/* Group VGOIO */ -#define GPIO_RSVD_13 141 -#define GPIO_RSVD_14 142 -#define GPIO_RSVD_15 143 -#define GPIO_RSVD_16 144 -#define GPIO_RSVD_17 145 -#define GPIO_RSVD_18 146 -#define GPIO_RSVD_19 147 -#define GPIO_RSVD_20 148 -#define GPIO_RSVD_21 149 -#define GPIO_RSVD_22 150 -#define GPIO_RSVD_23 151 -#define GPIO_RSVD_24 152 -#define GPIO_RSVD_25 153 -#define GPIO_RSVD_26 154 -#define GPIO_RSVD_27 155 -#define GPIO_RSVD_28 156 -#define GPIO_RSVD_29 157 -#define GPIO_RSVD_30 158 -#define GPIO_RSVD_31 159 -#define GPIO_RSVD_32 160 -#define GPIO_RSVD_33 161 -#define GPIO_RSVD_34 162 -#define GPIO_RSVD_35 163 -#define GPIO_RSVD_36 164 -#define GPIO_RSVD_37 165 -#define GPIO_RSVD_38 166 -#define GPIO_RSVD_39 167 -#define GPIO_RSVD_40 168 -#define GPIO_RSVD_41 169 -#define GPIO_RSVD_42 170 -#define GPIO_RSVD_43 171 -#define GPIO_RSVD_44 172 -#define GPIO_RSVD_45 173 -#define GPIO_RSVD_46 174 -#define GPIO_RSVD_47 175 -#define GPIO_RSVD_48 176 -#define GPIO_RSVD_49 177 -#define GPIO_RSVD_50 178 -#define GPIO_RSVD_51 179 -#define GPIO_RSVD_52 180 +#define GPP_H0 58 +#define GPP_H1 59 +#define GPP_H2 60 +#define GPP_H3 61 +#define GPP_H4 62 +#define GPP_H5 63 +#define GPP_H6 64 +#define GPP_H7 65 +#define GPP_H8 66 +#define GPP_H9 67 +#define GPP_H10 68 +#define GPP_H11 69 +#define GPP_H12 70 +#define GPP_H13 71 +#define GPP_H14 72 +#define GPP_H15 73 +#define GPP_H16 74 +#define GPP_H17 75 +#define GPP_H18 76 +#define GPP_H19 77 +#define GPP_H20 78 +#define GPP_H21 79 +#define GPP_H22 80 +#define GPP_H23 81 -#define NUM_GPIO_COM1_PADS (GPIO_RSVD_52 - GPP_D0 + 1) +/* Group D */ +#define GPP_D0 82 +#define GPP_D1 83 +#define GPP_D2 84 +#define GPP_D3 85 +#define GPP_D4 86 +#define GPP_D5 87 +#define GPP_D6 88 +#define GPP_D7 89 +#define GPP_D8 90 +#define GPP_D9 91 +#define GPP_D10 92 +#define GPP_D11 93 +#define GPP_D12 94 +#define GPP_D13 95 +#define GPP_D14 96 +#define GPP_D15 97 +#define GPP_D16 98 +#define GPP_D17 99 +#define GPP_D18 100 +#define GPP_D19 101 +#define GPIO_RSVD_2 102 -/* Group C */ -#define GPP_C0 181 -#define GPP_C1 182 -#define GPP_C2 183 -#define GPP_C3 184 -#define GPP_C4 185 -#define GPP_C5 186 -#define GPP_C6 187 -#define GPP_C7 188 -#define GPP_C8 189 -#define GPP_C9 190 -#define GPP_C10 191 -#define GPP_C11 192 -#define GPP_C12 193 -#define GPP_C13 194 -#define GPP_C14 195 -#define GPP_C15 196 -#define GPP_C16 197 -#define GPP_C17 198 -#define GPP_C18 199 -#define GPP_C19 200 -#define GPP_C20 201 -#define GPP_C21 202 -#define GPP_C22 203 -#define GPP_C23 204 -/* Group E */ -#define GPP_E0 205 -#define GPP_E1 206 -#define GPP_E2 207 -#define GPP_E3 208 -#define GPP_E4 209 -#define GPP_E5 210 -#define GPP_E6 211 -#define GPP_E7 212 -#define GPP_E8 213 -#define GPP_E9 214 -#define GPP_E10 215 -#define GPP_E11 216 -#define GPP_E12 217 -#define GPP_E13 218 -#define GPP_E14 219 -#define GPP_E15 220 -#define GPP_E16 221 -#define GPP_E17 222 -#define GPP_E18 223 -#define GPP_E19 224 -#define GPP_E20 225 -#define GPP_E21 226 -#define GPP_E22 227 -#define GPP_E23 228 -/* Group Jtag */ -#define GPIO_RSVD_53 229 -#define GPIO_RSVD_54 230 -#define GPIO_RSVD_55 231 -#define GPIO_RSVD_56 232 -#define GPIO_RSVD_57 233 -#define GPIO_RSVD_58 234 -#define GPIO_RSVD_59 235 -#define GPIO_RSVD_60 236 -#define GPIO_RSVD_61 237 -/* Group HVMOS */ -#define GPIO_RSVD_62 238 -#define GPIO_RSVD_63 239 -#define GPIO_RSVD_64 240 -#define GPIO_RSVD_65 241 -#define GPIO_RSVD_66 242 -#define GPIO_RSVD_67 243 +/* Group F */ +#define GPP_F0 103 +#define GPP_F1 104 +#define GPP_F2 105 +#define GPP_F3 106 +#define GPP_F4 107 +#define GPP_F5 108 +#define GPP_F6 109 +#define GPP_F7 110 +#define GPP_F8 111 +#define GPP_F9 112 +#define GPP_F10 113 +#define GPP_F11 114 +#define GPP_F12 115 +#define GPP_F13 116 +#define GPP_F14 117 +#define GPP_F15 118 +#define GPP_F16 119 +#define GPP_F17 120 +#define GPP_F18 121 +#define GPP_F19 122 + +#define NUM_GPIO_COM1_PADS (GPP_F19 - GPP_H0 + 1) -#define NUM_GPIO_COM4_PADS (GPIO_RSVD_67 - GPP_C0 + 1) /* Group GPD */ -#define GPD0 244 -#define GPD1 245 -#define GPD2 246 -#define GPD3 247 -#define GPD4 248 -#define GPD5 249 -#define GPD6 250 -#define GPD7 251 -#define GPD8 252 -#define GPD9 253 -#define GPD10 254 -#define GPD11 255 +#define GPD0 123 +#define GPD1 124 +#define GPD2 125 +#define GPD3 126 +#define GPD4 127 +#define GPD5 128 +#define GPD6 129 +#define GPD7 130 +#define GPD8 131 +#define GPD9 132 +#define GPD10 133 +#define GPD11 134 #define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) -/* Group AZA */ -#define HDA_BCLK 256 -#define HDA_RSTB 257 -#define HDA_SYNC 258 -#define HDA_SDO 259 -#define HDA_SDI_0 260 -#define HDA_SDI_1 261 -#define SSP1_SFRM 262 -#define SSP1_TXD 263 -/* Group CPU */ -#define GPIO_RSVD_68 264 -#define GPIO_RSVD_69 265 -#define GPIO_RSVD_70 266 -#define GPIO_RSVD_71 267 -#define GPIO_RSVD_72 268 -#define GPIO_RSVD_73 269 -#define GPIO_RSVD_74 270 -#define GPIO_RSVD_75 271 -#define GPIO_RSVD_76 272 -#define GPIO_RSVD_77 273 -#define GPIO_RSVD_78 274 +/* Group C */ +#define GPP_C0 135 +#define GPP_C1 136 +#define GPP_C2 137 +#define GPP_C3 138 +#define GPP_C4 139 +#define GPP_C5 140 +#define GPP_C6 141 +#define GPP_C7 142 +#define GPP_C8 143 +#define GPP_C9 144 +#define GPP_C10 145 +#define GPP_C11 146 +#define GPP_C12 147 +#define GPP_C13 148 +#define GPP_C14 149 +#define GPP_C15 150 +#define GPP_C16 151 +#define GPP_C17 152 +#define GPP_C18 153 +#define GPP_C19 154 +#define GPP_C20 155 +#define GPP_C21 156 +#define GPP_C22 157 +#define GPP_C23 158 +#define GPIO_RSVD_3 159 +#define GPIO_RSVD_4 160 +#define GPIO_RSVD_5 161 +#define GPIO_RSVD_6 162 +#define GPIO_RSVD_7 163 +#define GPIO_RSVD_8 164 + +/* Group E */ +#define GPP_E0 165 +#define GPP_E1 166 +#define GPP_E2 167 +#define GPP_E3 168 +#define GPP_E4 169 +#define GPP_E5 170 +#define GPP_E6 171 +#define GPP_E7 172 +#define GPP_E8 173 +#define GPP_E9 174 +#define GPP_E10 175 +#define GPP_E11 176 +#define GPP_E12 177 +#define GPP_E13 178 +#define GPP_E14 179 +#define GPP_E15 180 +#define GPP_E16 181 +#define GPP_E17 182 +#define GPP_E18 183 +#define GPP_E19 184 +#define GPP_E20 185 +#define GPP_E21 186 +#define GPP_E22 187 +#define GPP_E23 188 + +#define NUM_GPIO_COM4_PADS (GPP_E23 - GPP_C0 + 1) + +/* Group R*/ +#define GPP_R0 189 +#define GPP_R1 190 +#define GPP_R2 191 +#define GPP_R3 192 +#define GPP_R4 193 +#define GPP_R5 194 +#define GPP_R6 195 +#define GPP_R7 196 + +/* Group S */ +#define GPP_S0 197 +#define GPP_S1 198 +#define GPP_S2 199 +#define GPP_S3 200 +#define GPP_S4 201 +#define GPP_S5 202 +#define GPP_S6 203 +#define GPP_S7 204 -#define NUM_GPIO_COM3_PADS (GPIO_RSVD_78 - HDA_BCLK + 1) +#define NUM_GPIO_COM5_PADS (GPP_S7 - GPP_R0 + 1) -#define TOTAL_PADS 275 +#define TOTAL_PADS 205 #endif diff --git a/src/soc/intel/icelake/include/soc/pcr_ids.h b/src/soc/intel/icelake/include/soc/pcr_ids.h index 4cfb2946d0..a6ad30b617 100644 --- a/src/soc/intel/icelake/include/soc/pcr_ids.h +++ b/src/soc/intel/icelake/include/soc/pcr_ids.h @@ -24,7 +24,6 @@ #define PID_GPIOCOM0 0x6e #define PID_GPIOCOM1 0x6d #define PID_GPIOCOM2 0x6c -#define PID_GPIOCOM3 0x6b #define PID_GPIOCOM4 0x6a #define PID_GPIOCOM5 0x69 diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h index 9418c73bfe..448dbb5564 100644 --- a/src/soc/intel/icelake/include/soc/pmc.h +++ b/src/soc/intel/icelake/include/soc/pmc.h @@ -115,15 +115,17 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -#define PMC_GPP_A 0x0 +#define PMC_GPP_G 0x0 #define PMC_GPP_B 0x1 -#define PMC_GPP_C 0xD -#define PMC_GPP_D 0x4 -#define PMC_GPP_E 0xE -#define PMC_GPP_F 0x5 -#define PMC_GPP_G 0x2 +#define PMC_GPP_A 0x2 +#define PMC_GPP_R 0x3 +#define PMC_GPP_S 0x4 +#define PMC_GPD 0x5 #define PMC_GPP_H 0x6 -#define PMC_GPD 0xA +#define PMC_GPP_D 0x7 +#define PMC_GPP_F 0x8 +#define PMC_GPP_C 0xA +#define PMC_GPP_E 0xB #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) |