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-rw-r--r--src/soc/intel/icelake/graphics.c19
1 files changed, 0 insertions, 19 deletions
diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c
index 4f5d573c8b..0ee340ce3b 100644
--- a/src/soc/intel/icelake/graphics.c
+++ b/src/soc/intel/icelake/graphics.c
@@ -19,7 +19,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
-#include <drivers/intel/gma/i915_reg.h>
#include <drivers/intel/gma/opregion.h>
#include <intelblocks/graphics.h>
#include <types.h>
@@ -31,24 +30,6 @@ uintptr_t fsp_soc_get_igd_bar(void)
void graphics_soc_init(struct device *dev)
{
- uint32_t ddi_buf_ctl;
-
- /* Skip IGD GT programming */
- if (CONFIG(SKIP_GRAPHICS_ENABLING))
- return;
-
- /*
- * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
- * This will allow the kernel to use 4-lane eDP links properly
- * if the VBIOS or GOP driver do not execute.
- */
- ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
- if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
- ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED |
- DDI_BUF_IS_IDLE);
- graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
- }
-
/*
* GFX PEIM module inside FSP binary is taking care of graphics
* initialization based on RUN_FSP_GOP Kconfig