3 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c
index c1e6dd0d4a..e061cda2f0 100644
--- a/src/soc/intel/icelake/finalize.c
+++ b/src/soc/intel/icelake/finalize.c
@@ -87,6 +87,8 @@ static void pch_finalize(void)
 	}
 
 	pch_handle_sideband(config);
+
+	pmc_clear_pmcon_sts();
 }
 
 static void soc_finalize(void *unused)
diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h
index 9caf49fa9a..44888ec747 100644
--- a/src/soc/intel/icelake/include/soc/pm.h
+++ b/src/soc/intel/icelake/include/soc/pm.h
@@ -168,5 +168,8 @@ uint16_t smbus_tco_regs(void);
 /* Set the DISB after DRAM init */
 void pmc_set_disb(void);
 
+/* Clear PMCON status bits */
+void pmc_clear_pmcon_sts(void);
+
 #endif /* !defined(__ACPI__) */
 #endif
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index 96ff52d122..e1b1665368 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -141,6 +141,20 @@ void pmc_set_disb(void)
 	write8(addr, disb_val);
 }
 
+void pmc_clear_pmcon_sts(void)
+{
+	uint32_t reg_val;
+	uint8_t *addr;
+	addr = pmc_mmio_regs();
+
+	reg_val = read32(addr + GEN_PMCON_A);
+	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
+	 * while retaining MS4V write-1-to-clear bit */
+	reg_val &= ~(MS4V);
+
+	write32((addr + GEN_PMCON_A), reg_val);
+}
+
 /*
  * PMC controller gets hidden from PCI bus
  * during FSP-Silicon init call. Hence PWRMBASE