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-rw-r--r--src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl76
-rw-r--r--src/soc/intel/jasperlake/acpi/gpio.asl155
-rw-r--r--src/soc/intel/jasperlake/acpi/gpio_op.asl139
-rw-r--r--src/soc/intel/jasperlake/acpi/ipu.asl22
-rw-r--r--src/soc/intel/jasperlake/acpi/ish.asl21
-rw-r--r--src/soc/intel/jasperlake/acpi/pch_glan.asl26
-rw-r--r--src/soc/intel/jasperlake/acpi/pch_hda.asl82
-rw-r--r--src/soc/intel/jasperlake/acpi/pci_irqs.asl20
-rw-r--r--src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl141
-rw-r--r--src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl167
-rw-r--r--src/soc/intel/jasperlake/acpi/pcie.asl313
-rw-r--r--src/soc/intel/jasperlake/acpi/platform.asl32
-rw-r--r--src/soc/intel/jasperlake/acpi/pmc.asl31
-rw-r--r--src/soc/intel/jasperlake/acpi/scs.asl133
-rw-r--r--src/soc/intel/jasperlake/acpi/serialio.asl93
-rw-r--r--src/soc/intel/jasperlake/acpi/smbus.asl20
-rw-r--r--src/soc/intel/jasperlake/acpi/southbridge.asl61
-rw-r--r--src/soc/intel/jasperlake/acpi/xhci.asl19
-rw-r--r--src/soc/intel/jasperlake/acpi/xhci_jsl.asl62
-rw-r--r--src/soc/intel/jasperlake/acpi/xhci_tgl.asl62
20 files changed, 1675 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl
new file mode 100644
index 0000000000..4f08cd78bd
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define R_ICLK_PCR_CAMERA1 0x8000
+#define B_ICLK_PCR_FREQUENCY 0x1
+#define B_ICLK_PCR_REQUEST 0x2
+
+/* The clock control registers for each IMGCLK are offset by 0xC */
+#define B_ICLK_PCR_OFFSET 0xC
+
+Scope (\_SB.PCI0) {
+
+ /* IsCLK PCH base register for clock settings */
+ Name (ICKB, 0)
+ Store (PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, ICKB)
+
+ /*
+ * Arg0 : Clock Number
+ * Return : Offset of register to control the clock in Arg0
+ *
+ */
+ Method (OFST, 0x1, NotSerialized)
+ {
+ Return (ICKB + (Arg0 * B_ICLK_PCR_OFFSET))
+ }
+
+ /*
+ * Helper function for Read And OR Write
+ * Arg0 : source and destination
+ * Arg1 : And data
+ * Arg2 : Or data
+ */
+ Method (RAOW, 0x3, Serialized)
+ {
+ OperationRegion (ICLK, SystemMemory, OFST(Arg0), 4)
+ Field (ICLK, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ Local0 = VAL0
+ VAL0 = Local0 & Arg1 | Arg2
+ }
+
+ /*
+ * Clock control Method
+ * Arg0: Clock source select(0: IMGCLKOUT_0, 1: IMGCLKOUT_1, 2: IMGCLKOUT_2, 3: IMGCLKOUT_3,
+ * 4: IMGCLKOUT_4, 5: IMGCLKOUT_5)
+ * Arg1: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz)
+ */
+ Method (MCON, 0x2, NotSerialized)
+ {
+ /* Set Clock Frequency */
+ RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1)
+
+ /* Enable Clock */
+ RAOW (Arg0, ~B_ICLK_PCR_REQUEST, B_ICLK_PCR_REQUEST)
+ }
+
+ Method (MCOF, 0x1, NotSerialized)
+ {
+ /* Disable Clock */
+ RAOW (Arg0, ~B_ICLK_PCR_REQUEST, 0)
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl
new file mode 100644
index 0000000000..9bf0c6032f
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/gpio.asl
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <soc/gpio_defs.h>
+#include <soc/irq.h>
+#include <soc/pcr_ids.h>
+#include <intelblocks/gpio.h>
+#include "gpio_op.asl"
+
+Device (GCM0)
+{
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 0)
+ Name (_DDN, "GPIO Controller Community 0")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+ BAS0 = ^^PCRB (PID_GPIOCOM0)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
+
+Device (GCM1)
+{
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 1)
+ Name (_DDN, "GPIO Controller Community 1")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+ BAS1 = ^^PCRB (PID_GPIOCOM1)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
+
+Device (GCM4)
+{
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 4)
+ Name (_DDN, "GPIO Controller Community 4")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+ BAS4 = ^^PCRB (PID_GPIOCOM4)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
+
+Device (GCM5)
+{
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 5)
+ Name (_DDN, "GPIO Controller Community 5")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+ BAS5 = ^^PCRB (PID_GPIOCOM5)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
+
+/*
+ * Get GPIO DW0 Address
+ * Arg0 - GPIO Number
+ */
+Method (GADD, 1, NotSerialized)
+{
+ /* GPIO Community 0 */
+ If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END)
+ {
+ Local0 = PID_GPIOCOM0
+ Local1 = Arg0 - GPIO_COM0_START
+ }
+ /* GPIO Community 1 */
+ If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END)
+ {
+ Local0 = PID_GPIOCOM1
+ Local1 = Arg0 - GPIO_COM1_START
+ }
+ /* GPIO Community 2 */
+ If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END)
+ {
+ Local0 = PID_GPIOCOM2
+ Local1 = Arg0 - GPIO_COM2_START
+ }
+ /* GPIO Community 4 */
+ If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END)
+ {
+ Local0 = PID_GPIOCOM4
+ Local1 = Arg0 - GPIO_COM4_START
+ }
+ /* GPIO Community 05*/
+ If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END)
+ {
+ Local0 = PID_GPIOCOM5
+ Local1 = Arg0 - GPIO_COM5_START
+ }
+
+ Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
+ Return (Local2)
+}
diff --git a/src/soc/intel/jasperlake/acpi/gpio_op.asl b/src/soc/intel/jasperlake/acpi/gpio_op.asl
new file mode 100644
index 0000000000..4444c09a5b
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/gpio_op.asl
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Get GPIO Value
+ * Arg0 - GPIO Number
+ */
+Method (GRXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (PAD_CFG0_RX_STATE, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0)
+
+ Return (Local0)
+}
+
+/*
+ * Get GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (GTXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (PAD_CFG0_TX_STATE, VAL0, Local0)
+
+ Return (Local0)
+}
+
+/*
+ * Set GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (STXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ Or (PAD_CFG0_TX_STATE, VAL0, VAL0)
+}
+
+/*
+ * Clear GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (CTXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (Not (PAD_CFG0_TX_STATE), VAL0, VAL0)
+}
+
+/*
+ * Set Pad mode
+ * Arg0 - GPIO Number
+ * Arg1 - Pad mode
+ * 0 = GPIO control pad
+ * 1 = Native Function 1
+ * 2 = Native Function 2
+ * 3 = Native Function 3
+ */
+Method (GPMO, 2, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ Store (VAL0, Local0)
+ And (Not (PAD_CFG0_MODE_MASK), Local0, Local0)
+ And (ShiftLeft (Arg1, PAD_CFG0_MODE_SHIFT, Arg1), PAD_CFG0_MODE_MASK, Arg1)
+ Or (Local0, Arg1, VAL0)
+}
+
+/*
+ * Enable/Disable Tx buffer
+ * Arg0 - GPIO Number
+ * Arg1 - TxBuffer state
+ * 0 = Disable Tx Buffer
+ * 1 = Enable Tx Buffer
+ */
+Method (GTXE, 2, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+
+ If (LEqual (Arg1, 1)) {
+ And (Not (PAD_CFG0_TX_DISABLE), VAL0, VAL0)
+ } ElseIf (LEqual (Arg1, 0)){
+ Or (PAD_CFG0_TX_DISABLE, VAL0, VAL0)
+ }
+}
+
+/*
+ * Enable/Disable Rx buffer
+ * Arg0 - GPIO Number
+ * Arg1 - RxBuffer state
+ * 0 = Disable Rx Buffer
+ * 1 = Enable Rx Buffer
+ */
+Method (GRXE, 2, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+
+ If (LEqual (Arg1, 1)) {
+ And (Not (PAD_CFG0_RX_DISABLE), VAL0, VAL0)
+ } ElseIf (LEqual (Arg1, 0)){
+ Or (PAD_CFG0_RX_DISABLE, VAL0, VAL0)
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/ipu.asl b/src/soc/intel/jasperlake/acpi/ipu.asl
new file mode 100644
index 0000000000..5711644bcb
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/ipu.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0)
+{
+ Device (IPU0)
+ {
+ Name (_ADR, 0x00050000)
+ Name (_DDN, "Camera and Imaging Subsystem")
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/ish.asl b/src/soc/intel/jasperlake/acpi/ish.asl
new file mode 100644
index 0000000000..ee3f1a3fdf
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/ish.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Integrated Sensor Hub Controller 0:12.0 */
+
+Device (ISHB)
+{
+ Name (_ADR, 0x00120000)
+ Name (_DDN, "Integrated Sensor Hub Controller")
+}
diff --git a/src/soc/intel/jasperlake/acpi/pch_glan.asl b/src/soc/intel/jasperlake/acpi/pch_glan.asl
new file mode 100644
index 0000000000..2d9d960565
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pch_glan.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Gigabit Ethernet Controller 0:1f.6 */
+
+Device (GLAN)
+{
+ Name (_ADR, 0x001f0006)
+
+ Name (_S0W, 3)
+
+ Name (_PRW, Package() {GPE0_PME_B0, 4})
+
+ Method (_DSW, 3) {}
+}
diff --git a/src/soc/intel/jasperlake/acpi/pch_hda.asl b/src/soc/intel/jasperlake/acpi/pch_hda.asl
new file mode 100644
index 0000000000..0d10d2deb5
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pch_hda.asl
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Audio Controller - Device 31, Function 3 */
+
+Device (HDAS)
+{
+ Name (_ADR, 0x001f0003)
+ Name (_DDN, "Audio Controller")
+ Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
+
+ /* Device is D3 wake capable */
+ Name (_S0W, 3)
+
+ /* NHLT Table Address populated from GNVS values */
+ Name (NBUF, ResourceTemplate () {
+ QWordMemory (ResourceConsumer, PosDecode, MinFixed,
+ MaxFixed, NonCacheable, ReadOnly,
+ 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
+ })
+
+ /*
+ * Device Specific Method
+ * Arg0 - UUID
+ * Arg1 - Revision
+ * Arg2 - Function Index
+ */
+ Method (_DSM, 4)
+ {
+ If (LEqual (Arg0, ^UUID)) {
+ /*
+ * Function 0: Function Support Query
+ * Returns a bitmask of functions supported.
+ */
+ If (LEqual (Arg2, Zero)) {
+ /*
+ * NHLT Query only supported for revision 1 and
+ * if NHLT address and length are set in NVS.
+ */
+ If (LAnd (LEqual (Arg1, One),
+ LAnd (LNotEqual (NHLA, Zero),
+ LNotEqual (NHLL, Zero)))) {
+ Return (Buffer (One) { 0x03 })
+ } Else {
+ Return (Buffer (One) { 0x01 })
+ }
+ }
+
+ /*
+ * Function 1: Query NHLT memory address used by
+ * Intel Offload Engine Driver to discover any non-HDA
+ * devices that are supported by the DSP.
+ *
+ * Returns a pointer to NHLT table in memory.
+ */
+ If (LEqual (Arg2, One)) {
+ CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
+ CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
+ CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
+
+ Store (NHLA, NBAS)
+ Store (NHLA, NMAS)
+ Store (NHLL, NLEN)
+
+ Return (NBUF)
+ }
+ }
+
+ Return (Buffer (One) { 0x00 })
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs.asl b/src/soc/intel/jasperlake/acpi/pci_irqs.asl
new file mode 100644
index 0000000000..474a6d6c1e
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pci_irqs.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
+ #include "pci_irqs_tgl.asl"
+#else
+ #include "pci_irqs_jsl.asl"
+#endif
diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl
new file mode 100644
index 0000000000..086282e733
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl
@@ -0,0 +1,141 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/irq.h>
+
+Name (PICP, Package () {
+ /* cAVS, SMBus, GbE, Northpeak */
+ Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ },
+ Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ },
+ Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ },
+ Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ },
+ /* SerialIo */
+ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+ Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
+ Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
+ Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
+ /* PCI Express Port 1-8 */
+ Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
+ Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
+ Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
+ Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
+ Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
+ Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
+ Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
+ Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
+ /* eMMC */
+ Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
+ /* SerialIo */
+ Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
+ Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+ Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
+ /* SATA controller */
+ Package(){0x0017FFFF, 0, 0, SATA_IRQ },
+ /* CSME (HECI, IDE-R, Keyboard and Text redirection */
+ Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
+ Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
+ Package(){0x0016FFFF, 2, 0, IDER_IRQ },
+ Package(){0x0016FFFF, 3, 0, KT_IRQ },
+ Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
+ Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
+ /* SerialIo */
+ Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+ Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+ Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+ Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
+ /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
+ Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
+ Package(){0x0014FFFF, 1, 0, OTG_IRQ },
+ Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
+ Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
+ Package(){0x0014FFFF, 5, 0, SD_IRQ },
+ /* SerialIo */
+ Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
+ /* SA IGFX Device */
+ Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
+ /* SA Thermal Device */
+ Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
+ /* SA IPU Device */
+ Package(){0x0005FFFF, 0, 0, IPU_IRQ },
+ /* SA GNA Device */
+ Package(){0x0008FFFF, 0, 0, GNA_IRQ },
+})
+
+Name (PICN, Package () {
+ /* D31: cAVS, SMBus, GbE, Northpeak */
+ Package () { 0x001FFFFF, 3, 0, 11 },
+ Package () { 0x001FFFFF, 4, 0, 10 },
+ Package () { 0x001FFFFF, 6, 0, 11 },
+ Package () { 0x001FFFFF, 7, 0, 11 },
+ /* D30: SerialIo */
+ Package () {0x001EFFFF, 0, 0, 11 },
+ Package () {0x001EFFFF, 1, 0, 10 },
+ Package () {0x001EFFFF, 2, 0, 11 },
+ Package () {0x001EFFFF, 3, 0, 11 },
+ /* D28: PCI Express Port 1-8 */
+ Package () { 0x001CFFFF, 0, 0, 11 },
+ Package () { 0x001CFFFF, 1, 0, 10 },
+ Package () { 0x001CFFFF, 2, 0, 11 },
+ Package () { 0x001CFFFF, 3, 0, 11 },
+ Package () { 0x001CFFFF, 4, 0, 11 },
+ Package () { 0x001CFFFF, 5, 0, 10 },
+ Package () { 0x001CFFFF, 6, 0, 11 },
+ Package () { 0x001CFFFF, 7, 0, 11 },
+ /* D26: eMMC */
+ Package(){0x001AFFFF, 0, 0, 11 },
+ /* D25: SerialIo */
+ Package () {0x0019FFFF, 0, 0, 11 },
+ Package () {0x0019FFFF, 1, 0, 10 },
+ Package () {0x0019FFFF, 2, 0, 11 },
+ /* D23: SATA controller */
+ Package () { 0x0017FFFF, 0, 0, 11 },
+ /* D22: CSME (HECI, IDE-R, KT redirection */
+ Package () { 0x0016FFFF, 0, 0, 11 },
+ Package () { 0x0016FFFF, 1, 0, 10 },
+ Package () { 0x0016FFFF, 2, 0, 11 },
+ Package () { 0x0016FFFF, 3, 0, 11 },
+ Package () { 0x0016FFFF, 4, 0, 11 },
+ Package () { 0x0016FFFF, 5, 0, 11 },
+ /* D21: SerialIo */
+ Package () {0x0015FFFF, 0, 0, 11 },
+ Package () {0x0015FFFF, 1, 0, 10 },
+ Package () {0x0015FFFF, 2, 0, 11 },
+ Package () {0x0015FFFF, 3, 0, 11 },
+ /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
+ Package () { 0x0014FFFF, 0, 0, 11 },
+ Package () { 0x0014FFFF, 1, 0, 10 },
+ Package () { 0x0014FFFF, 2, 0, 11 },
+ Package () { 0x0014FFFF, 3, 0, 11 },
+ Package () { 0x0014FFFF, 5, 0, 11 },
+ /* D18: SerialIo */
+ Package () {0x0012FFFF, 6, 0, 11 },
+ /* SA IGFX Device */
+ Package () {0x0002FFFF, 0, 0, 11 },
+ /* SA Thermal Device */
+ Package () { 0x0004FFFF, 0, 0, 11 },
+ /* SA IPU Device */
+ Package () { 0x0005FFFF, 0, 0, 11 },
+ /* SA GNA Device */
+ Package () { 0x0008FFFF, 0, 0, 11 },
+})
+
+Method (_PRT)
+{
+ If (PICM) {
+ Return (^PICP)
+ } Else {
+ Return (^PICN)
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl
new file mode 100644
index 0000000000..7f632ba32e
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/irq.h>
+
+Name (PICP, Package () {
+ /* D31:HSA, SMBUS, TraceHUB */
+ Package(){0x001FFFFF, 3, 0, HDA_IRQ },
+ Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
+ Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
+ /* D30: UART0, UART1, SPI0, SPI1 */
+ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+ Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
+ Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
+ Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
+ /* D29: RP9 ~ RP12 */
+ Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
+ Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
+ Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
+ Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
+ /* D28: RP1 ~ RP8 */
+ Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
+ Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
+ Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
+ Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
+ Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
+ Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
+ Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
+ Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
+ /* D25: I2C4, I2C5, UART2 */
+ Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
+ Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+ Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
+ /* D23: SATA */
+ Package(){0x0017FFFF, 0, 0, SATA_IRQ },
+ /* D22: CSME */
+ Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
+ Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
+ Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
+ Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
+ /* D21: I2C0 ~ I2C3 */
+ Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+ Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+ Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+ Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
+ /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
+ Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
+ Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
+ Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
+ /* D19: SPI3 */
+ Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
+ /* D18: ISH, SPI2 */
+ Package(){0x0012FFFF, 0, 0, ISH_IRQ },
+ Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
+ /* D16: CNVI_BT, TCH0, TCH1 */
+ Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
+ Package(){0x0010FFFF, 6, 0, THC0_IRQ },
+ Package(){0x0010FFFF, 7, 0, THC1_IRQ },
+ /* D13: xHCI, xDCI */
+ Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
+ Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
+ /* D8: GNA */
+ Package(){0x0008FFFF, 0, 0, GNA_IRQ },
+ /* D7: TBT PCIe */
+ Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
+ Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
+ Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
+ Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
+ /* D6: PEG60 */
+ Package(){0x0006FFFF, 0, 0, PEG_IRQ },
+ /* D5: IPU Device */
+ Package(){0x0005FFFF, 0, 0, IPU_IRQ },
+ /* D4: Thermal Device */
+ Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
+ /* D2: IGFX */
+ Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
+})
+
+Name (PICN, Package () {
+ /* D31:HSA, SMBUS, TraceHUB*/
+ Package () { 0x001FFFFF, 3, 0, 11 },
+ Package () { 0x001FFFFF, 4, 0, 11 },
+ Package () { 0x001FFFFF, 7, 0, 11 },
+ /* D30: UART0, UART1, SPI0, SPI1 */
+ Package () { 0x001EFFFF, 0, 0, 11 },
+ Package () { 0x001EFFFF, 1, 0, 10 },
+ Package () { 0x001EFFFF, 2, 0, 11 },
+ Package () { 0x001EFFFF, 3, 0, 11 },
+ /* D29: RP9 ~ RP12 */
+ Package () { 0x001DFFFF, 0, 0, 11 },
+ Package () { 0x001DFFFF, 1, 0, 10 },
+ Package () { 0x001DFFFF, 2, 0, 11 },
+ Package () { 0x001DFFFF, 3, 0, 11 },
+ /* D28: RP1 ~ RP8 */
+ Package () { 0x001CFFFF, 0, 0, 11 },
+ Package () { 0x001CFFFF, 1, 0, 10 },
+ Package () { 0x001CFFFF, 2, 0, 11 },
+ Package () { 0x001CFFFF, 3, 0, 11 },
+ Package () { 0x001CFFFF, 4, 0, 11 },
+ Package () { 0x001CFFFF, 5, 0, 10 },
+ Package () { 0x001CFFFF, 6, 0, 11 },
+ Package () { 0x001CFFFF, 7, 0, 11 },
+ /* D25: I2C4, I2C5, UART2 */
+ Package(){0x0019FFFF, 0, 0, 11 },
+ Package(){0x0019FFFF, 1, 0, 10 },
+ Package(){0x0019FFFF, 2, 0, 11 },
+ /* D23: SATA */
+ Package () { 0x0017FFFF, 0, 0, 11 },
+ /* D22: CSME */
+ Package(){0x0016FFFF, 0, 0, 11 },
+ Package(){0x0016FFFF, 1, 0, 10 },
+ Package(){0x0016FFFF, 4, 0, 11 },
+ Package(){0x0016FFFF, 5, 0, 11 },
+ /* D21: I2C0 ~ I2C3 */
+ Package(){0x0015FFFF, 0, 0, 11 },
+ Package(){0x0015FFFF, 1, 0, 10 },
+ Package(){0x0015FFFF, 2, 0, 11 },
+ Package(){0x0015FFFF, 3, 0, 11 },
+ /* D19: SPI3 */
+ Package(){0x0013FFFF, 0, 0, 11 },
+ /* D18: ISH, SPI2 */
+ Package(){0x0012FFFF, 0, 0, 11 },
+ Package(){0x0012FFFF, 6, 0, 11 },,
+ /* D16: CNVI_BT, TCH0, TCH1 */
+ Package(){0x0010FFFF, 2, 0, 11 },
+ Package(){0x0010FFFF, 6, 0, 11 },
+ Package(){0x0010FFFF, 7, 0, 10 },
+ /* D13: xHCI, xDCI */
+ Package(){0x000DFFFF, 0, 0, 11 },
+ Package(){0x000DFFFF, 1, 0, 10 },
+ /* D8: GNA */
+ Package(){0x0008FFFF, 0, 0, 11 },
+ /* D7: TBT PCIe */
+ Package(){0x0007FFFF, 0, 0, 11 },
+ Package(){0x0007FFFF, 1, 0, 10 },
+ Package(){0x0007FFFF, 2, 0, 11 },
+ Package(){0x0007FFFF, 3, 0, 11 },
+ /* D6: PEG60 */
+ Package(){0x0006FFFF, 0, 0, 11 },
+ /* D5: IPU Device */
+ Package(){0x0005FFFF, 0, 0, 11 },
+ /* D4: Thermal Device */
+ Package(){0x0004FFFF, 0, 0, 11 },
+ /* D2: IGFX */
+ Package(){0x0002FFFF, 0, 0, 11 },
+})
+
+Method (_PRT)
+{
+ If (PICM) {
+ Return (^PICP)
+ } Else {
+ Return (^PICN)
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/pcie.asl b/src/soc/intel/jasperlake/acpi/pcie.asl
new file mode 100644
index 0000000000..53ae316413
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pcie.asl
@@ -0,0 +1,313 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel PCH PCIe support */
+
+Method (IRQM, 1, Serialized) {
+
+ /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
+ Name (IQAA, Package () {
+ Package () { 0x0000ffff, 0, 0, 16 },
+ Package () { 0x0000ffff, 1, 0, 17 },
+ Package () { 0x0000ffff, 2, 0, 18 },
+ Package () { 0x0000ffff, 3, 0, 19 } })
+ Name (IQAP, Package () {
+ Package () { 0x0000ffff, 0, 0, 11 },
+ Package () { 0x0000ffff, 1, 0, 10 },
+ Package () { 0x0000ffff, 2, 0, 11 },
+ Package () { 0x0000ffff, 3, 0, 11 } })
+
+ /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
+ Name (IQBA, Package () {
+ Package () { 0x0000ffff, 0, 0, 17 },
+ Package () { 0x0000ffff, 1, 0, 18 },
+ Package () { 0x0000ffff, 2, 0, 19 },
+ Package () { 0x0000ffff, 3, 0, 16 } })
+ Name (IQBP, Package () {
+ Package () { 0x0000ffff, 0, 0, 10 },
+ Package () { 0x0000ffff, 1, 0, 11 },
+ Package () { 0x0000ffff, 2, 0, 11 },
+ Package () { 0x0000ffff, 3, 0, 11 } })
+
+ /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
+ Name (IQCA, Package () {
+ Package () { 0x0000ffff, 0, 0, 18 },
+ Package () { 0x0000ffff, 1, 0, 19 },
+ Package () { 0x0000ffff, 2, 0, 16 },
+ Package () { 0x0000ffff, 3, 0, 17 } })
+ Name (IQCP, Package () {
+ Package () { 0x0000ffff, 0, 0, 11 },
+ Package () { 0x0000ffff, 1, 0, 11 },
+ Package () { 0x0000ffff, 2, 0, 11 },
+ Package () { 0x0000ffff, 3, 0, 10 } })
+
+ /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
+ Name (IQDA, Package () {
+ Package () { 0x0000ffff, 0, 0, 19 },
+ Package () { 0x0000ffff, 1, 0, 16 },
+ Package () { 0x0000ffff, 2, 0, 17 },
+ Package () { 0x0000ffff, 3, 0, 18 } })
+ Name (IQDP, Package () {
+ Package () { 0x0000ffff, 0, 0, 11 },
+ Package () { 0x0000ffff, 1, 0, 11 },
+ Package () { 0x0000ffff, 2, 0, 10 },
+ Package () { 0x0000ffff, 3, 0, 11 } })
+
+ Switch (ToInteger (Arg0))
+ {
+ Case (Package () { 1, 5, 9, 13 }) {
+ If (PICM) {
+ Return (IQAA)
+ } Else {
+ Return (IQAP)
+ }
+ }
+
+ Case (Package () { 2, 6, 10, 14 }) {
+ If (PICM) {
+ Return (IQBA)
+ } Else {
+ Return (IQBP)
+ }
+ }
+
+ Case (Package () { 3, 7, 11, 15 }) {
+ If (PICM) {
+ Return (IQCA)
+ } Else {
+ Return (IQCP)
+ }
+ }
+
+ Case (Package () { 4, 8, 12, 16 }) {
+ If (PICM) {
+ Return (IQDA)
+ } Else {
+ Return (IQDP)
+ }
+ }
+
+ Default {
+ If (PICM) {
+ Return (IQDA)
+ } Else {
+ Return (IQDP)
+ }
+ }
+ }
+}
+
+Device (RP01)
+{
+ Name (_ADR, 0x001C0000)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP02)
+{
+ Name (_ADR, 0x001C0001)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP03)
+{
+ Name (_ADR, 0x001C0002)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP04)
+{
+ Name (_ADR, 0x001C0003)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP05)
+{
+ Name (_ADR, 0x001C0004)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP06)
+{
+ Name (_ADR, 0x001C0005)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP07)
+{
+ Name (_ADR, 0x001C0006)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP08)
+{
+ Name (_ADR, 0x001C0007)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP09)
+{
+ Name (_ADR, 0x001D0000)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP10)
+{
+ Name (_ADR, 0x001D0001)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP11)
+{
+ Name (_ADR, 0x001D0002)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP12)
+{
+ Name (_ADR, 0x001D0003)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/platform.asl b/src/soc/intel/jasperlake/acpi/platform.asl
new file mode 100644
index 0000000000..682a7b93d8
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/platform.asl
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+/* Generic indicator for sleep state */
+#include <soc/intel/common/acpi/platform.asl>
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method (_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice. */
+ Store (Arg0, PICM)
+}
diff --git a/src/soc/intel/jasperlake/acpi/pmc.asl b/src/soc/intel/jasperlake/acpi/pmc.asl
new file mode 100644
index 0000000000..6dd2d35354
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pmc.asl
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+Scope (\_SB.PCI0) {
+
+ Device (PMC)
+ {
+ Name (_HID, "INTC1026")
+ Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
+ /*
+ * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF.
+ * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR.
+ */
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000)
+ })
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl
new file mode 100644
index 0000000000..83da7e0f06
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/scs.asl
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/pcr_ids.h>
+
+Scope (\_SB.PCI0) {
+
+ /*
+ * Clear register 0x1C20/0x4820
+ * Arg0 - PCR Port ID
+ */
+ Method(SCSC, 1, Serialized)
+ {
+ PCRA (Arg0, 0x1C20, 0x0)
+ PCRA (Arg0, 0x4820, 0x0)
+ }
+
+ /* EMMC */
+ Device(PEMC) {
+ Name(_ADR, 0x001A0000)
+ Name (_DDN, "eMMC Controller")
+ Name (TEMP, 0)
+
+ OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
+ Field(SCSR, WordAcc, NoLock, Preserve) {
+ Offset (0x84), /* PMECTRLSTATUS */
+ PMCR, 16,
+ Offset (0xA2), /* PG_CONFIG */
+ , 2,
+ PGEN, 1, /* PG_ENABLE */
+ }
+
+ Method(_INI) {
+ /* Clear register 0x1C20/0x4820 */
+ SCSC (PID_EMMC)
+ }
+
+ Method(_PS0, 0, Serialized) {
+ Stall (50) // Sleep 50 us
+
+ Store(0, PGEN) // Disable PG
+
+ /* Clear register 0x1C20/0x4820 */
+ SCSC (PID_EMMC)
+
+ /* Set Power State to D0 */
+ And (PMCR, 0xFFFC, PMCR)
+ Store (PMCR, TEMP)
+ }
+
+ Method(_PS3, 0, Serialized) {
+ Store(1, PGEN) // Enable PG
+
+ /* Set Power State to D3 */
+ Or (PMCR, 0x0003, PMCR)
+ Store (PMCR, TEMP)
+ }
+
+ Device (CARD)
+ {
+ Name (_ADR, 0x00000008)
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (0)
+ }
+ }
+ }
+
+ /* SD CARD */
+ Device (SDXC)
+ {
+ Name (_ADR, 0x00140005)
+ Name (_DDN, "SD Controller")
+ Name (TEMP, 0)
+
+ OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
+ Field (SDPC, WordAcc, NoLock, Preserve)
+ {
+ Offset (0x84), /* PMECTRLSTATUS */
+ PMCR, 16,
+ Offset (0xA2), /* PG_CONFIG */
+ , 2,
+ PGEN, 1, /* PG_ENABLE */
+ }
+
+ Method(_INI)
+ {
+ /* Clear register 0x1C20/0x4820 */
+ SCSC (PID_SDX)
+ }
+
+ Method (_PS0, 0, Serialized)
+ {
+ Store (0, PGEN) /* Disable PG */
+
+ /* Clear register 0x1C20/0x4820 */
+ SCSC (PID_SDX)
+
+ /* Set Power State to D0 */
+ And (PMCR, 0xFFFC, PMCR)
+ Store (PMCR, TEMP)
+ }
+
+ Method (_PS3, 0, Serialized)
+ {
+ Store (1, PGEN) /* Enable PG */
+
+ /* Set Power State to D3 */
+ Or (PMCR, 0x0003, PMCR)
+ Store (PMCR, TEMP)
+ }
+
+ Device (CARD)
+ {
+ Name (_ADR, 0x00000008)
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (1)
+ }
+ }
+ } /* Device (SDXC) */
+}
diff --git a/src/soc/intel/jasperlake/acpi/serialio.asl b/src/soc/intel/jasperlake/acpi/serialio.asl
new file mode 100644
index 0000000000..6fd135b437
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/serialio.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Serial IO Devices */
+
+Device (I2C0)
+{
+ Name (_ADR, 0x00150000)
+ Name (_DDN, "Serial IO I2C Controller 0")
+}
+
+Device (I2C1)
+{
+ Name (_ADR, 0x00150001)
+ Name (_DDN, "Serial IO I2C Controller 1")
+}
+
+Device (I2C2)
+{
+ Name (_ADR, 0x00150002)
+ Name (_DDN, "Serial IO I2C Controller 2")
+}
+
+Device (I2C3)
+{
+ Name (_ADR, 0x00150003)
+ Name (_DDN, "Serial IO I2C Controller 3")
+}
+
+Device (I2C4)
+{
+ Name (_ADR, 0x00190000)
+ Name (_DDN, "Serial IO I2C Controller 4")
+}
+
+Device (I2C5)
+{
+ Name (_ADR, 0x00190001)
+ Name (_DDN, "Serial IO I2C Controller 5")
+}
+
+Device (SPI0)
+{
+ Name (_ADR, 0x001e0002)
+ Name (_DDN, "Serial IO SPI Controller 0")
+}
+
+Device (SPI1)
+{
+ Name (_ADR, 0x001e0003)
+ Name (_DDN, "Serial IO SPI Controller 1")
+}
+
+Device (SPI2)
+{
+ Name (_ADR, 0x00120006)
+ Name (_DDN, "Serial IO SPI Controller 2")
+}
+
+Device (SPI3)
+{
+ Name (_ADR, 0x00130000)
+ Name (_DDN, "Serial IO SPI Controller 3")
+}
+
+Device (UAR0)
+{
+ Name (_ADR, 0x001e0000)
+ Name (_DDN, "Serial IO UART Controller 0")
+}
+
+Device (UAR1)
+{
+ Name (_ADR, 0x001e0001)
+ Name (_DDN, "Serial IO UART Controller 1")
+}
+
+Device (UAR2)
+{
+ Name (_ADR, 0x00190002)
+ Name (_DDN, "Serial IO UART Controller 2")
+}
diff --git a/src/soc/intel/jasperlake/acpi/smbus.asl b/src/soc/intel/jasperlake/acpi/smbus.asl
new file mode 100644
index 0000000000..f273e3669d
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/smbus.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel SMBus Controller 0:1f.4 */
+
+Device (SBUS)
+{
+ Name (_ADR, 0x001f0004)
+}
diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl
new file mode 100644
index 0000000000..6329340392
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/southbridge.asl
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/itss.h>
+#include <intelblocks/pcr.h>
+#include <soc/itss.h>
+#include <soc/pcr_ids.h>
+
+/* PCI IRQ assignment */
+#include "pci_irqs.asl"
+
+/* PCR access */
+#include <soc/intel/common/acpi/pcr.asl>
+
+/* PCH clock */
+#include "camera_clock_ctl.asl"
+
+/* GPIO controller */
+#include "gpio.asl"
+
+/* ESPI 0:1f.0 */
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
+
+/* PCH HDA */
+#include "pch_hda.asl"
+
+/* PCIE Ports */
+#include "pcie.asl"
+
+/* pmc 0:1f.2 */
+#include "pmc.asl"
+
+/* Serial IO */
+#include "serialio.asl"
+
+/* SMBus 0:1f.4 */
+#include "smbus.asl"
+
+/* ISH 0:12.0 */
+#include "ish.asl"
+
+/* USB XHCI 0:14.0 */
+#include "xhci.asl"
+
+/* PCI _OSC */
+#include <soc/intel/common/acpi/pci_osc.asl>
+
+/* PMC Core*/
+#include <soc/intel/common/block/acpi/acpi/pmc.asl>
diff --git a/src/soc/intel/jasperlake/acpi/xhci.asl b/src/soc/intel/jasperlake/acpi/xhci.asl
new file mode 100644
index 0000000000..9baf67ac5a
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/xhci.asl
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
+ #include "xhci_tgl.asl"
+#else
+ #include "xhci_jsl.asl"
+#endif
diff --git a/src/soc/intel/jasperlake/acpi/xhci_jsl.asl b/src/soc/intel/jasperlake/acpi/xhci_jsl.asl
new file mode 100644
index 0000000000..41be89ace1
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/xhci_jsl.asl
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpe.h>
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+ Name (_ADR, 0x00140000)
+
+ Name (_PRW, Package () { GPE0_PME_B0, 3 })
+
+ Name (_S3D, 3) /* D3 supported in S3 */
+ Name (_S0W, 3) /* D3 can wake device in S0 */
+ Name (_S3W, 3) /* D3 can wake system from S3 */
+
+ Method (_PS0, 0, Serialized)
+ {
+
+ }
+
+ Method (_PS3, 0, Serialized)
+ {
+
+ }
+
+ /* Root Hub for Jasperlake PCH */
+ Device (RHUB)
+ {
+ Name (_ADR, Zero)
+
+ /* USB2 */
+ Device (HS01) { Name (_ADR, 1) }
+ Device (HS02) { Name (_ADR, 2) }
+ Device (HS03) { Name (_ADR, 3) }
+ Device (HS04) { Name (_ADR, 4) }
+ Device (HS05) { Name (_ADR, 5) }
+ Device (HS06) { Name (_ADR, 6) }
+ Device (HS07) { Name (_ADR, 7) }
+ Device (HS08) { Name (_ADR, 8) }
+
+ /* USB3 */
+ Device (SS01) { Name (_ADR, 9) }
+ Device (SS02) { Name (_ADR, 10) }
+ Device (SS03) { Name (_ADR, 11) }
+ Device (SS04) { Name (_ADR, 12) }
+ Device (SS05) { Name (_ADR, 13) }
+ Device (SS06) { Name (_ADR, 14) }
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/xhci_tgl.asl b/src/soc/intel/jasperlake/acpi/xhci_tgl.asl
new file mode 100644
index 0000000000..b97f52052b
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/xhci_tgl.asl
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpe.h>
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+ Name (_ADR, 0x00140000)
+
+ Name (_PRW, Package () { GPE0_PME_B0, 3 })
+
+ Name (_S3D, 3) /* D3 supported in S3 */
+ Name (_S0W, 3) /* D3 can wake device in S0 */
+ Name (_S3W, 3) /* D3 can wake system from S3 */
+
+ Method (_PS0, 0, Serialized)
+ {
+
+ }
+
+ Method (_PS3, 0, Serialized)
+ {
+
+ }
+
+ /* Root Hub for Tigerlake-LP PCH */
+ Device (RHUB)
+ {
+ Name (_ADR, Zero)
+
+ /* USB2 */
+ Device (HS01) { Name (_ADR, 1) }
+ Device (HS02) { Name (_ADR, 2) }
+ Device (HS03) { Name (_ADR, 3) }
+ Device (HS04) { Name (_ADR, 4) }
+ Device (HS05) { Name (_ADR, 5) }
+ Device (HS06) { Name (_ADR, 6) }
+ Device (HS07) { Name (_ADR, 7) }
+ Device (HS08) { Name (_ADR, 8) }
+ Device (HS09) { Name (_ADR, 9) }
+ Device (HS10) { Name (_ADR, 10) }
+
+ /* USB3 */
+ Device (SS01) { Name (_ADR, 13) }
+ Device (SS02) { Name (_ADR, 14) }
+ Device (SS03) { Name (_ADR, 15) }
+ Device (SS04) { Name (_ADR, 16) }
+ }
+}