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Diffstat (limited to 'src/soc/intel/jasperlake/chip.h')
-rw-r--r--src/soc/intel/jasperlake/chip.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 7a6a7fd0dd..d8ea560dfa 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -7,6 +7,7 @@
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
+#include <intelblocks/power_limit.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
#include <soc/gpio_defs.h>
@@ -26,6 +27,9 @@ struct soc_intel_jasperlake_config {
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
+ /* Common struct containing power limits configuration information */
+ struct soc_power_limits_config power_limits_config;
+
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form PMC_GPP_[A:U] or GPD. */
uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
@@ -145,8 +149,6 @@ struct soc_intel_jasperlake_config {
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
- /* PL2 Override value in Watts */
- uint32_t tdp_pl2_override;
/* Intel Speed Shift Technology */
uint8_t speed_shift_enable;