1 files changed, 36 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/gspi.c b/src/soc/intel/jasperlake/gspi.c
new file mode 100644
index 0000000000..1381fb2499
--- /dev/null
+++ b/src/soc/intel/jasperlake/gspi.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 11
+ */
+
+#include <intelblocks/gspi.h>
+#include <soc/pci_devs.h>
+
+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
+{
+	switch (gspi_bus) {
+	case 0:
+		return PCH_DEVFN_GSPI0;
+	case 1:
+		return PCH_DEVFN_GSPI1;
+	case 2:
+		return PCH_DEVFN_GSPI2;
+	}
+	return -1;
+}