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-rw-r--r--src/soc/intel/jasperlake/Kconfig232
-rw-r--r--src/soc/intel/jasperlake/Makefile.inc66
-rw-r--r--src/soc/intel/jasperlake/acpi.c343
-rw-r--r--src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl76
-rw-r--r--src/soc/intel/jasperlake/acpi/gpio.asl155
-rw-r--r--src/soc/intel/jasperlake/acpi/gpio_op.asl139
-rw-r--r--src/soc/intel/jasperlake/acpi/ipu.asl22
-rw-r--r--src/soc/intel/jasperlake/acpi/ish.asl21
-rw-r--r--src/soc/intel/jasperlake/acpi/pch_glan.asl26
-rw-r--r--src/soc/intel/jasperlake/acpi/pch_hda.asl82
-rw-r--r--src/soc/intel/jasperlake/acpi/pci_irqs.asl20
-rw-r--r--src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl141
-rw-r--r--src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl167
-rw-r--r--src/soc/intel/jasperlake/acpi/pcie.asl313
-rw-r--r--src/soc/intel/jasperlake/acpi/platform.asl32
-rw-r--r--src/soc/intel/jasperlake/acpi/pmc.asl31
-rw-r--r--src/soc/intel/jasperlake/acpi/scs.asl133
-rw-r--r--src/soc/intel/jasperlake/acpi/serialio.asl93
-rw-r--r--src/soc/intel/jasperlake/acpi/smbus.asl20
-rw-r--r--src/soc/intel/jasperlake/acpi/southbridge.asl61
-rw-r--r--src/soc/intel/jasperlake/acpi/xhci.asl19
-rw-r--r--src/soc/intel/jasperlake/acpi/xhci_jsl.asl62
-rw-r--r--src/soc/intel/jasperlake/acpi/xhci_tgl.asl62
-rw-r--r--src/soc/intel/jasperlake/bootblock/bootblock.c43
-rw-r--r--src/soc/intel/jasperlake/bootblock/cpu.c36
-rw-r--r--src/soc/intel/jasperlake/bootblock/pch.c194
-rw-r--r--src/soc/intel/jasperlake/bootblock/report_platform.c246
-rw-r--r--src/soc/intel/jasperlake/chip.c183
-rw-r--r--src/soc/intel/jasperlake/chip.h299
-rw-r--r--src/soc/intel/jasperlake/cpu.c267
-rw-r--r--src/soc/intel/jasperlake/elog.c130
-rw-r--r--src/soc/intel/jasperlake/espi.c247
-rw-r--r--src/soc/intel/jasperlake/finalize.c117
-rw-r--r--src/soc/intel/jasperlake/fsp_params_jsl.c191
-rw-r--r--src/soc/intel/jasperlake/fsp_params_tgl.c212
-rw-r--r--src/soc/intel/jasperlake/gpio_jsl.c210
-rw-r--r--src/soc/intel/jasperlake/gpio_tgl.c197
-rw-r--r--src/soc/intel/jasperlake/graphics.c93
-rw-r--r--src/soc/intel/jasperlake/gspi.c36
-rw-r--r--src/soc/intel/jasperlake/i2c.c61
-rw-r--r--src/soc/intel/jasperlake/include/soc/bootblock.h27
-rw-r--r--src/soc/intel/jasperlake/include/soc/cpu.h48
-rw-r--r--src/soc/intel/jasperlake/include/soc/espi.h58
-rw-r--r--src/soc/intel/jasperlake/include/soc/gpe.h133
-rw-r--r--src/soc/intel/jasperlake/include/soc/gpio.h38
-rw-r--r--src/soc/intel/jasperlake/include/soc/gpio_defs.h23
-rw-r--r--src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h272
-rw-r--r--src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h314
-rw-r--r--src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h23
-rw-r--r--src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h358
-rw-r--r--src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h394
-rw-r--r--src/soc/intel/jasperlake/include/soc/iomap.h131
-rw-r--r--src/soc/intel/jasperlake/include/soc/irq.h24
-rw-r--r--src/soc/intel/jasperlake/include/soc/irq_jsl.h86
-rw-r--r--src/soc/intel/jasperlake/include/soc/irq_tgl.h83
-rw-r--r--src/soc/intel/jasperlake/include/soc/itss.h25
-rw-r--r--src/soc/intel/jasperlake/include/soc/me.h55
-rw-r--r--src/soc/intel/jasperlake/include/soc/meminit_jsl.h124
-rw-r--r--src/soc/intel/jasperlake/include/soc/meminit_tgl.h69
-rw-r--r--src/soc/intel/jasperlake/include/soc/msr.h23
-rw-r--r--src/soc/intel/jasperlake/include/soc/nvs.h20
-rw-r--r--src/soc/intel/jasperlake/include/soc/p2sb.h29
-rw-r--r--src/soc/intel/jasperlake/include/soc/pch.h28
-rw-r--r--src/soc/intel/jasperlake/include/soc/pci_devs.h209
-rw-r--r--src/soc/intel/jasperlake/include/soc/pcr_ids.h49
-rw-r--r--src/soc/intel/jasperlake/include/soc/pm.h182
-rw-r--r--src/soc/intel/jasperlake/include/soc/pmc.h168
-rw-r--r--src/soc/intel/jasperlake/include/soc/ramstage.h26
-rw-r--r--src/soc/intel/jasperlake/include/soc/romstage.h32
-rw-r--r--src/soc/intel/jasperlake/include/soc/serialio.h48
-rw-r--r--src/soc/intel/jasperlake/include/soc/smbus.h47
-rw-r--r--src/soc/intel/jasperlake/include/soc/soc_chip.h20
-rw-r--r--src/soc/intel/jasperlake/include/soc/systemagent.h79
-rw-r--r--src/soc/intel/jasperlake/include/soc/usb.h151
-rw-r--r--src/soc/intel/jasperlake/lockdown.c77
-rw-r--r--src/soc/intel/jasperlake/meminit_jsl.c126
-rw-r--r--src/soc/intel/jasperlake/meminit_tgl.c163
-rw-r--r--src/soc/intel/jasperlake/p2sb.c48
-rw-r--r--src/soc/intel/jasperlake/pmc.c113
-rw-r--r--src/soc/intel/jasperlake/pmutil.c286
-rw-r--r--src/soc/intel/jasperlake/reset.c46
-rw-r--r--src/soc/intel/jasperlake/romstage/Makefile.inc20
-rw-r--r--src/soc/intel/jasperlake/romstage/fsp_params_jsl.c145
-rw-r--r--src/soc/intel/jasperlake/romstage/fsp_params_tgl.c208
-rw-r--r--src/soc/intel/jasperlake/romstage/pch.c26
-rw-r--r--src/soc/intel/jasperlake/romstage/romstage.c134
-rw-r--r--src/soc/intel/jasperlake/romstage/systemagent.c47
-rw-r--r--src/soc/intel/jasperlake/sd.c42
-rw-r--r--src/soc/intel/jasperlake/smihandler.c53
-rw-r--r--src/soc/intel/jasperlake/smmrelocate.c261
-rw-r--r--src/soc/intel/jasperlake/spi.c38
-rw-r--r--src/soc/intel/jasperlake/systemagent.c80
-rw-r--r--src/soc/intel/jasperlake/uart.c75
93 files changed, 10462 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
new file mode 100644
index 0000000000..ed2fece152
--- /dev/null
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -0,0 +1,232 @@
+config SOC_INTEL_TIGERLAKE_BASE_COPY
+ bool
+
+config SOC_INTEL_TIGERLAKE_COPY
+ bool
+ select SOC_INTEL_TIGERLAKE_BASE_COPY
+ #TODO - Enable INTEL_CAR_NEM_ENHANCED
+ select INTEL_CAR_NEM
+ help
+ Intel Tigerlake support
+
+config SOC_INTEL_JASPERLAKE_COPY
+ bool
+ select SOC_INTEL_TIGERLAKE_BASE_COPY
+ select INTEL_CAR_NEM
+ help
+ Intel Jasperlake support
+
+if SOC_INTEL_TIGERLAKE_BASE_COPY
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_VERSTAGE_X86_32
+ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
+ select BOOT_DEVICE_SUPPORTS_WRITES
+ select CACHE_MRC_SETTINGS
+ select COMMON_FADT
+ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+ select FSP_M_XIP
+ select GENERIC_GPIO_LIB
+ select HAVE_FSP_GOP
+ select INTEL_DESCRIPTOR_MODE_CAPABLE
+ select HAVE_SMI_HANDLER
+ select IDT_IN_EVERY_STAGE
+ select INTEL_GMA_ACPI
+ select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
+ select IOAPIC
+ select MRC_SETTINGS_PROTECT
+ select PARALLEL_MP
+ select PARALLEL_MP_AP_WORK
+ select MICROCODE_BLOB_UNDISCLOSED
+ select PLATFORM_USES_FSP2_1
+ select REG_SCRIPT
+ select SMP
+ select SOC_AHCI_PORT_IMPLEMENTED_INVERT
+ select PMC_GLOBAL_RESET_ENABLE_LOCK
+ select CPU_INTEL_COMMON_SMM
+ select SOC_INTEL_COMMON
+ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_BLOCK_ACPI
+ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
+ select SOC_INTEL_COMMON_BLOCK_CPU
+ select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
+ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
+ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
+ select SOC_INTEL_COMMON_BLOCK_HDA
+ select SOC_INTEL_COMMON_BLOCK_SA
+ select SOC_INTEL_COMMON_BLOCK_SMM
+ select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+ select SOC_INTEL_COMMON_PCH_BASE
+ select SOC_INTEL_COMMON_RESET
+ select SOC_INTEL_COMMON_BLOCK_CAR
+ select SSE2
+ select SUPPORT_CPU_UCODE_IN_CBFS
+ select TSC_MONOTONIC_TIMER
+ select UDELAY_TSC
+ select UDK_2017_BINDING
+ select DISPLAY_FSP_VERSION_INFO
+ select HECI_DISABLE_USING_SMM
+
+config DCACHE_RAM_BASE
+ default 0xfef00000
+
+config DCACHE_RAM_SIZE
+ default 0x80000
+ help
+ The size of the cache-as-ram region required during bootblock
+ and/or romstage.
+
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x40400 if SOC_INTEL_TIGERLAKE_COPY
+ default 0x30400 if SOC_INTEL_JASPERLAKE_COPY
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages. In the case of FSP_USES_CB_STACK default value will be
+ sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage
+ stack requirement (~1KiB).
+
+config FSP_TEMP_RAM_SIZE
+ hex
+ default 0x20000
+ help
+ The amount of anticipated heap usage in CAR by FSP.
+ Refer to Platform FSP integration guide document to know
+ the exact FSP requirement for Heap setup.
+
+config IFD_CHIPSET
+ string
+ default "jsl" if SOC_INTEL_JASPERLAKE_COPY
+ default "tgl" if SOC_INTEL_TIGERLAKE_COPY
+
+config IED_REGION_SIZE
+ hex
+ default 0x400000
+
+config HEAP_SIZE
+ hex
+ default 0x8000
+
+config MAX_ROOT_PORTS
+ int
+ default 8 if SOC_INTEL_JASPERLAKE_COPY
+ default 12 if SOC_INTEL_TIGERLAKE_COPY
+
+config MAX_PCIE_CLOCKS
+ int
+ default 7 if SOC_INTEL_TIGERLAKE_COPY
+ default 6 if SOC_INTEL_JASPERLAKE_COPY
+
+config SMM_TSEG_SIZE
+ hex
+ default 0x800000
+
+config SMM_RESERVED_SIZE
+ hex
+ default 0x200000
+
+config PCR_BASE_ADDRESS
+ hex
+ default 0xfd000000
+ help
+ This option allows you to select MMIO Base Address of sideband bus.
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xc0000000
+
+config CPU_BCLK_MHZ
+ int
+ default 100
+
+config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
+ int
+ default 120
+
+config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
+ int
+ default 133
+
+config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
+ int
+ default 3 if SOC_INTEL_JASPERLAKE_COPY
+ default 4 if SOC_INTEL_TIGERLAKE_COPY
+
+config SOC_INTEL_I2C_DEV_MAX
+ int
+ default 6
+
+config SOC_INTEL_UART_DEV_MAX
+ int
+ default 3
+
+config CONSOLE_UART_BASE_ADDRESS
+ hex
+ default 0xfe032000
+ depends on INTEL_LPSS_UART_FOR_CONSOLE
+
+# Clock divider parameters for 115200 baud rate
+# Baudrate = (UART source clcok * M) /(N *16)
+# TGL UART source clock: 120MHz
+# JSL UART source clock: 100MHz
+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
+ hex
+ default 0x30 if SOC_INTEL_JASPERLAKE_COPY
+ default 0x25a if SOC_INTEL_TIGERLAKE_COPY
+
+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
+ hex
+ default 0xc35 if SOC_INTEL_JASPERLAKE_COPY
+ default 0x7fff if SOC_INTEL_TIGERLAKE_COPY
+
+config CHROMEOS
+ select CHROMEOS_RAMOOPS_DYNAMIC
+
+config VBOOT
+ select VBOOT_SEPARATE_VERSTAGE
+ select VBOOT_MUST_REQUEST_DISPLAY
+ select VBOOT_STARTS_IN_BOOTBLOCK
+ select VBOOT_VBNV_CMOS
+ select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
+
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0xC000
+
+config CBFS_SIZE
+ hex
+ default 0x200000
+
+config FSP_HEADER_PATH
+ string "Location of FSP headers"
+ default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" if SOC_INTEL_JASPERLAKE_COPY
+ default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" if SOC_INTEL_TIGERLAKE_COPY
+
+config FSP_FD_PATH
+ string
+ depends on FSP_USE_REPO
+ default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE_COPY
+ default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE_COPY
+
+config SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT
+ int "Debug Consent for TGL"
+ # USB DBC is more common for developers so make this default to 3 if
+ # SOC_INTEL_DEBUG_CONSENT=y
+ default 3 if SOC_INTEL_DEBUG_CONSENT
+ default 0
+ help
+ This is to control debug interface on SOC.
+ Setting non-zero value will allow to use DBC or DCI to debug SOC.
+ PlatformDebugConsent in FspmUpd.h has the details.
+
+ Desired platform debug type are
+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
+ 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
+ 6:Enable (2-wire DCI OOB), 7:Manual
+endif
diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc
new file mode 100644
index 0000000000..b02dc10250
--- /dev/null
+++ b/src/soc/intel/jasperlake/Makefile.inc
@@ -0,0 +1,66 @@
+ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE_COPY),y)
+
+subdirs-y += romstage
+subdirs-y += ../../../cpu/intel/microcode
+subdirs-y += ../../../cpu/intel/turbo
+subdirs-y += ../../../cpu/x86/lapic
+subdirs-y += ../../../cpu/x86/mtrr
+subdirs-y += ../../../cpu/x86/smm
+subdirs-y += ../../../cpu/x86/tsc
+
+# all (bootblock, verstage, romstage, postcar, ramstage)
+all-y += gspi.c
+all-y += i2c.c
+all-y += pmutil.c
+all-y += spi.c
+all-y += uart.c
+
+bootblock-y += bootblock/bootblock.c
+bootblock-y += bootblock/cpu.c
+bootblock-y += bootblock/pch.c
+bootblock-y += bootblock/report_platform.c
+bootblock-y += espi.c
+bootblock-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
+bootblock-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
+bootblock-y += p2sb.c
+
+romstage-y += espi.c
+romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += meminit_tgl.c
+romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += meminit_jsl.c
+romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
+romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
+romstage-y += reset.c
+
+ramstage-y += acpi.c
+ramstage-y += chip.c
+ramstage-y += cpu.c
+ramstage-y += elog.c
+ramstage-y += espi.c
+ramstage-y += finalize.c
+ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += fsp_params_tgl.c
+ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += fsp_params_jsl.c
+ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
+ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
+ramstage-y += graphics.c
+ramstage-y += lockdown.c
+ramstage-y += p2sb.c
+ramstage-y += pmc.c
+ramstage-y += reset.c
+ramstage-y += smmrelocate.c
+ramstage-y += systemagent.c
+ramstage-y += sd.c
+
+smm-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
+smm-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
+smm-y += p2sb.c
+smm-y += pmc.c
+smm-y += pmutil.c
+smm-y += smihandler.c
+smm-y += uart.c
+
+verstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/tigerlake
+CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include
+
+endif
diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c
new file mode 100644
index 0000000000..23fd970500
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi.c
@@ -0,0 +1,343 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <device/mmio.h>
+#include <arch/smp/mpspec.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/cpulib.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/acpi.h>
+#include <soc/cpu.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/soc_chip.h>
+#include <soc/systemagent.h>
+#include <string.h>
+#include <wrdd.h>
+
+/*
+ * List of supported C-states in this processor.
+ */
+enum {
+ C_STATE_C0, /* 0 */
+ C_STATE_C1, /* 1 */
+ C_STATE_C1E, /* 2 */
+ C_STATE_C6_SHORT_LAT, /* 3 */
+ C_STATE_C6_LONG_LAT, /* 4 */
+ C_STATE_C7_SHORT_LAT, /* 5 */
+ C_STATE_C7_LONG_LAT, /* 6 */
+ C_STATE_C7S_SHORT_LAT, /* 7 */
+ C_STATE_C7S_LONG_LAT, /* 8 */
+ C_STATE_C8, /* 9 */
+ C_STATE_C9, /* 10 */
+ C_STATE_C10, /* 11 */
+ NUM_C_STATES
+};
+
+#define MWAIT_RES(state, sub_state) \
+ { \
+ .addrl = (((state) << 4) | (sub_state)), \
+ .space_id = ACPI_ADDRESS_SPACE_FIXED, \
+ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
+ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
+ .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
+ }
+
+static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
+ [C_STATE_C0] = {},
+ [C_STATE_C1] = {
+ .latency = 0,
+ .power = C1_POWER,
+ .resource = MWAIT_RES(0, 0),
+ },
+ [C_STATE_C1E] = {
+ .latency = 0,
+ .power = C1_POWER,
+ .resource = MWAIT_RES(0, 1),
+ },
+ [C_STATE_C6_SHORT_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+ .power = C6_POWER,
+ .resource = MWAIT_RES(2, 0),
+ },
+ [C_STATE_C6_LONG_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+ .power = C6_POWER,
+ .resource = MWAIT_RES(2, 1),
+ },
+ [C_STATE_C7_SHORT_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+ .power = C7_POWER,
+ .resource = MWAIT_RES(3, 0),
+ },
+ [C_STATE_C7_LONG_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+ .power = C7_POWER,
+ .resource = MWAIT_RES(3, 1),
+ },
+ [C_STATE_C7S_SHORT_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+ .power = C7_POWER,
+ .resource = MWAIT_RES(3, 2),
+ },
+ [C_STATE_C7S_LONG_LAT] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+ .power = C7_POWER,
+ .resource = MWAIT_RES(3, 3),
+ },
+ [C_STATE_C8] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+ .power = C8_POWER,
+ .resource = MWAIT_RES(4, 0),
+ },
+ [C_STATE_C9] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+ .power = C9_POWER,
+ .resource = MWAIT_RES(5, 0),
+ },
+ [C_STATE_C10] = {
+ .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+ .power = C10_POWER,
+ .resource = MWAIT_RES(6, 0),
+ },
+};
+
+static int cstate_set_non_s0ix[] = {
+ C_STATE_C1E,
+ C_STATE_C6_LONG_LAT,
+ C_STATE_C7S_LONG_LAT
+};
+
+static int cstate_set_s0ix[] = {
+ C_STATE_C1E,
+ C_STATE_C7S_LONG_LAT,
+ C_STATE_C10
+};
+
+acpi_cstate_t *soc_get_cstate_map(size_t *entries)
+{
+ static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
+ ARRAY_SIZE(cstate_set_non_s0ix))];
+ int *set;
+ int i;
+
+ config_t *config = config_of_soc();
+
+ int is_s0ix_enable = config->s0ix_enable;
+
+ if (is_s0ix_enable) {
+ *entries = ARRAY_SIZE(cstate_set_s0ix);
+ set = cstate_set_s0ix;
+ } else {
+ *entries = ARRAY_SIZE(cstate_set_non_s0ix);
+ set = cstate_set_non_s0ix;
+ }
+
+ for (i = 0; i < *entries; i++) {
+ memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
+ map[i].ctype = i + 1;
+ }
+ return map;
+}
+
+void soc_power_states_generation(int core_id, int cores_per_package)
+{
+ config_t *config = config_of_soc();
+
+ if (config->eist_enable)
+ /* Generate P-state tables */
+ generate_p_state_entries(core_id, cores_per_package);
+}
+
+void soc_fill_fadt(acpi_fadt_t *fadt)
+{
+ const uint16_t pmbase = ACPI_BASE_ADDRESS;
+
+ config_t *config = config_of_soc();
+
+ fadt->pm_tmr_blk = pmbase + PM1_TMR;
+ fadt->pm_tmr_len = 4;
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ if (config->s0ix_enable)
+ fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
+}
+
+uint32_t soc_read_sci_irq_select(void)
+{
+ uintptr_t pmc_bar = soc_read_pmc_base();
+ return read32((void *)pmc_bar + IRQ_REG);
+}
+
+static unsigned long soc_fill_dmar(unsigned long current)
+{
+ const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
+ uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
+ bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
+
+ if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) {
+ unsigned long tmp = current;
+
+ current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
+ current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+
+ acpi_dmar_drhd_fixup(tmp, current);
+ }
+
+ const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
+ uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
+ bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
+
+ if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) {
+ unsigned long tmp = current;
+
+ current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
+ current += acpi_create_dmar_ds_pci(current, 0, 5, 0);
+
+ acpi_dmar_drhd_fixup(tmp, current);
+ }
+
+ uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
+ bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
+
+ if (vtvc0bar && vtvc0en) {
+ const unsigned long tmp = current;
+
+ current += acpi_create_dmar_drhd(current,
+ DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
+ current += acpi_create_dmar_ds_ioapic(current,
+ 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
+ V_P2SB_CFG_IBDF_FUNC);
+ current += acpi_create_dmar_ds_msi_hpet(current,
+ 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
+ V_P2SB_CFG_HBDF_FUNC);
+
+ acpi_dmar_drhd_fixup(tmp, current);
+ }
+
+ /* TCSS Thunderbolt root ports */
+ for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) {
+ uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK;
+ bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED;
+ if (tbtbar && tbten) {
+ unsigned long tmp = current;
+
+ current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
+ current += acpi_create_dmar_ds_pci(current, 0, 7, i);
+
+ acpi_dmar_drhd_fixup(tmp, current);
+ }
+ }
+
+ /* Add RMRR entry */
+ const unsigned long tmp = current;
+ current += acpi_create_dmar_rmrr(current, 0,
+ sa_get_gsm_base(), sa_get_tolud_base() - 1);
+ current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+ acpi_dmar_rmrr_fixup(tmp, current);
+
+ return current;
+}
+
+unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current,
+ struct acpi_rsdp *rsdp)
+{
+ acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
+
+ /*
+ * Create DMAR table only if we have VT-d capability and FSP does not override its
+ * feature.
+ */
+ if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
+ !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
+ return current;
+
+ printk(BIOS_DEBUG, "ACPI: * DMAR\n");
+ acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar);
+ current += dmar->header.length;
+ current = acpi_align_current(current);
+ acpi_add_table(rsdp, dmar);
+
+ return current;
+}
+
+void acpi_create_gnvs(struct global_nvs_t *gnvs)
+{
+ config_t *config = config_of_soc();
+
+ /* Set unknown wake source */
+ gnvs->pm1i = -1;
+
+ /* CPU core count */
+ gnvs->pcnt = dev_count_cpu();
+
+ if (CONFIG(CONSOLE_CBMEM))
+ /* Update the mem console pointer. */
+ gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
+
+ if (CONFIG(CHROMEOS)) {
+ /* Initialize Verified Boot data */
+ chromeos_init_chromeos_acpi(&(gnvs->chromeos));
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+ gnvs->chromeos.vbt2 = google_ec_running_ro() ?
+ ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
+ } else
+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+ }
+
+ /* Enable DPTF based on mainboard configuration */
+ gnvs->dpte = config->dptf_enable;
+
+ /* Fill in the Wifi Region id */
+ gnvs->cid1 = wifi_regulatory_domain();
+
+ /* Set USB2/USB3 wake enable bitmaps. */
+ gnvs->u2we = config->usb2_wake_enable_bitmap;
+ gnvs->u3we = config->usb3_wake_enable_bitmap;
+
+ /* Fill in Above 4GB MMIO resource */
+ sa_fill_gnvs(gnvs);
+}
+
+uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
+ const struct chipset_power_state *ps)
+{
+ /*
+ * WAK_STS bit is set when the system is in one of the sleep states
+ * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
+ * this bit, the PMC will transition the system to the ON state and
+ * can only be set by hardware and can only be cleared by writing a one
+ * to this bit position.
+ */
+
+ generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
+ return generic_pm1_en;
+}
+
+int soc_madt_sci_irq_polarity(int sci)
+{
+ return MP_IRQ_POLARITY_HIGH;
+}
diff --git a/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl
new file mode 100644
index 0000000000..4f08cd78bd
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define R_ICLK_PCR_CAMERA1 0x8000
+#define B_ICLK_PCR_FREQUENCY 0x1
+#define B_ICLK_PCR_REQUEST 0x2
+
+/* The clock control registers for each IMGCLK are offset by 0xC */
+#define B_ICLK_PCR_OFFSET 0xC
+
+Scope (\_SB.PCI0) {
+
+ /* IsCLK PCH base register for clock settings */
+ Name (ICKB, 0)
+ Store (PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, ICKB)
+
+ /*
+ * Arg0 : Clock Number
+ * Return : Offset of register to control the clock in Arg0
+ *
+ */
+ Method (OFST, 0x1, NotSerialized)
+ {
+ Return (ICKB + (Arg0 * B_ICLK_PCR_OFFSET))
+ }
+
+ /*
+ * Helper function for Read And OR Write
+ * Arg0 : source and destination
+ * Arg1 : And data
+ * Arg2 : Or data
+ */
+ Method (RAOW, 0x3, Serialized)
+ {
+ OperationRegion (ICLK, SystemMemory, OFST(Arg0), 4)
+ Field (ICLK, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ Local0 = VAL0
+ VAL0 = Local0 & Arg1 | Arg2
+ }
+
+ /*
+ * Clock control Method
+ * Arg0: Clock source select(0: IMGCLKOUT_0, 1: IMGCLKOUT_1, 2: IMGCLKOUT_2, 3: IMGCLKOUT_3,
+ * 4: IMGCLKOUT_4, 5: IMGCLKOUT_5)
+ * Arg1: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz)
+ */
+ Method (MCON, 0x2, NotSerialized)
+ {
+ /* Set Clock Frequency */
+ RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1)
+
+ /* Enable Clock */
+ RAOW (Arg0, ~B_ICLK_PCR_REQUEST, B_ICLK_PCR_REQUEST)
+ }
+
+ Method (MCOF, 0x1, NotSerialized)
+ {
+ /* Disable Clock */
+ RAOW (Arg0, ~B_ICLK_PCR_REQUEST, 0)
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl
new file mode 100644
index 0000000000..9bf0c6032f
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/gpio.asl
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <soc/gpio_defs.h>
+#include <soc/irq.h>
+#include <soc/pcr_ids.h>
+#include <intelblocks/gpio.h>
+#include "gpio_op.asl"
+
+Device (GCM0)
+{
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 0)
+ Name (_DDN, "GPIO Controller Community 0")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+ BAS0 = ^^PCRB (PID_GPIOCOM0)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
+
+Device (GCM1)
+{
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 1)
+ Name (_DDN, "GPIO Controller Community 1")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+ BAS1 = ^^PCRB (PID_GPIOCOM1)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
+
+Device (GCM4)
+{
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 4)
+ Name (_DDN, "GPIO Controller Community 4")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+ BAS4 = ^^PCRB (PID_GPIOCOM4)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
+
+Device (GCM5)
+{
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 5)
+ Name (_DDN, "GPIO Controller Community 5")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+ BAS5 = ^^PCRB (PID_GPIOCOM5)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
+
+/*
+ * Get GPIO DW0 Address
+ * Arg0 - GPIO Number
+ */
+Method (GADD, 1, NotSerialized)
+{
+ /* GPIO Community 0 */
+ If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END)
+ {
+ Local0 = PID_GPIOCOM0
+ Local1 = Arg0 - GPIO_COM0_START
+ }
+ /* GPIO Community 1 */
+ If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END)
+ {
+ Local0 = PID_GPIOCOM1
+ Local1 = Arg0 - GPIO_COM1_START
+ }
+ /* GPIO Community 2 */
+ If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END)
+ {
+ Local0 = PID_GPIOCOM2
+ Local1 = Arg0 - GPIO_COM2_START
+ }
+ /* GPIO Community 4 */
+ If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END)
+ {
+ Local0 = PID_GPIOCOM4
+ Local1 = Arg0 - GPIO_COM4_START
+ }
+ /* GPIO Community 05*/
+ If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END)
+ {
+ Local0 = PID_GPIOCOM5
+ Local1 = Arg0 - GPIO_COM5_START
+ }
+
+ Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
+ Return (Local2)
+}
diff --git a/src/soc/intel/jasperlake/acpi/gpio_op.asl b/src/soc/intel/jasperlake/acpi/gpio_op.asl
new file mode 100644
index 0000000000..4444c09a5b
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/gpio_op.asl
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Get GPIO Value
+ * Arg0 - GPIO Number
+ */
+Method (GRXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (PAD_CFG0_RX_STATE, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0)
+
+ Return (Local0)
+}
+
+/*
+ * Get GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (GTXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (PAD_CFG0_TX_STATE, VAL0, Local0)
+
+ Return (Local0)
+}
+
+/*
+ * Set GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (STXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ Or (PAD_CFG0_TX_STATE, VAL0, VAL0)
+}
+
+/*
+ * Clear GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (CTXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (Not (PAD_CFG0_TX_STATE), VAL0, VAL0)
+}
+
+/*
+ * Set Pad mode
+ * Arg0 - GPIO Number
+ * Arg1 - Pad mode
+ * 0 = GPIO control pad
+ * 1 = Native Function 1
+ * 2 = Native Function 2
+ * 3 = Native Function 3
+ */
+Method (GPMO, 2, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ Store (VAL0, Local0)
+ And (Not (PAD_CFG0_MODE_MASK), Local0, Local0)
+ And (ShiftLeft (Arg1, PAD_CFG0_MODE_SHIFT, Arg1), PAD_CFG0_MODE_MASK, Arg1)
+ Or (Local0, Arg1, VAL0)
+}
+
+/*
+ * Enable/Disable Tx buffer
+ * Arg0 - GPIO Number
+ * Arg1 - TxBuffer state
+ * 0 = Disable Tx Buffer
+ * 1 = Enable Tx Buffer
+ */
+Method (GTXE, 2, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+
+ If (LEqual (Arg1, 1)) {
+ And (Not (PAD_CFG0_TX_DISABLE), VAL0, VAL0)
+ } ElseIf (LEqual (Arg1, 0)){
+ Or (PAD_CFG0_TX_DISABLE, VAL0, VAL0)
+ }
+}
+
+/*
+ * Enable/Disable Rx buffer
+ * Arg0 - GPIO Number
+ * Arg1 - RxBuffer state
+ * 0 = Disable Rx Buffer
+ * 1 = Enable Rx Buffer
+ */
+Method (GRXE, 2, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+
+ If (LEqual (Arg1, 1)) {
+ And (Not (PAD_CFG0_RX_DISABLE), VAL0, VAL0)
+ } ElseIf (LEqual (Arg1, 0)){
+ Or (PAD_CFG0_RX_DISABLE, VAL0, VAL0)
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/ipu.asl b/src/soc/intel/jasperlake/acpi/ipu.asl
new file mode 100644
index 0000000000..5711644bcb
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/ipu.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0)
+{
+ Device (IPU0)
+ {
+ Name (_ADR, 0x00050000)
+ Name (_DDN, "Camera and Imaging Subsystem")
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/ish.asl b/src/soc/intel/jasperlake/acpi/ish.asl
new file mode 100644
index 0000000000..ee3f1a3fdf
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/ish.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Integrated Sensor Hub Controller 0:12.0 */
+
+Device (ISHB)
+{
+ Name (_ADR, 0x00120000)
+ Name (_DDN, "Integrated Sensor Hub Controller")
+}
diff --git a/src/soc/intel/jasperlake/acpi/pch_glan.asl b/src/soc/intel/jasperlake/acpi/pch_glan.asl
new file mode 100644
index 0000000000..2d9d960565
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pch_glan.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Gigabit Ethernet Controller 0:1f.6 */
+
+Device (GLAN)
+{
+ Name (_ADR, 0x001f0006)
+
+ Name (_S0W, 3)
+
+ Name (_PRW, Package() {GPE0_PME_B0, 4})
+
+ Method (_DSW, 3) {}
+}
diff --git a/src/soc/intel/jasperlake/acpi/pch_hda.asl b/src/soc/intel/jasperlake/acpi/pch_hda.asl
new file mode 100644
index 0000000000..0d10d2deb5
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pch_hda.asl
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Audio Controller - Device 31, Function 3 */
+
+Device (HDAS)
+{
+ Name (_ADR, 0x001f0003)
+ Name (_DDN, "Audio Controller")
+ Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
+
+ /* Device is D3 wake capable */
+ Name (_S0W, 3)
+
+ /* NHLT Table Address populated from GNVS values */
+ Name (NBUF, ResourceTemplate () {
+ QWordMemory (ResourceConsumer, PosDecode, MinFixed,
+ MaxFixed, NonCacheable, ReadOnly,
+ 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
+ })
+
+ /*
+ * Device Specific Method
+ * Arg0 - UUID
+ * Arg1 - Revision
+ * Arg2 - Function Index
+ */
+ Method (_DSM, 4)
+ {
+ If (LEqual (Arg0, ^UUID)) {
+ /*
+ * Function 0: Function Support Query
+ * Returns a bitmask of functions supported.
+ */
+ If (LEqual (Arg2, Zero)) {
+ /*
+ * NHLT Query only supported for revision 1 and
+ * if NHLT address and length are set in NVS.
+ */
+ If (LAnd (LEqual (Arg1, One),
+ LAnd (LNotEqual (NHLA, Zero),
+ LNotEqual (NHLL, Zero)))) {
+ Return (Buffer (One) { 0x03 })
+ } Else {
+ Return (Buffer (One) { 0x01 })
+ }
+ }
+
+ /*
+ * Function 1: Query NHLT memory address used by
+ * Intel Offload Engine Driver to discover any non-HDA
+ * devices that are supported by the DSP.
+ *
+ * Returns a pointer to NHLT table in memory.
+ */
+ If (LEqual (Arg2, One)) {
+ CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
+ CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
+ CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
+
+ Store (NHLA, NBAS)
+ Store (NHLA, NMAS)
+ Store (NHLL, NLEN)
+
+ Return (NBUF)
+ }
+ }
+
+ Return (Buffer (One) { 0x00 })
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs.asl b/src/soc/intel/jasperlake/acpi/pci_irqs.asl
new file mode 100644
index 0000000000..474a6d6c1e
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pci_irqs.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
+ #include "pci_irqs_tgl.asl"
+#else
+ #include "pci_irqs_jsl.asl"
+#endif
diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl
new file mode 100644
index 0000000000..086282e733
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl
@@ -0,0 +1,141 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/irq.h>
+
+Name (PICP, Package () {
+ /* cAVS, SMBus, GbE, Northpeak */
+ Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ },
+ Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ },
+ Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ },
+ Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ },
+ /* SerialIo */
+ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+ Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
+ Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
+ Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
+ /* PCI Express Port 1-8 */
+ Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
+ Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
+ Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
+ Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
+ Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
+ Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
+ Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
+ Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
+ /* eMMC */
+ Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
+ /* SerialIo */
+ Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
+ Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+ Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
+ /* SATA controller */
+ Package(){0x0017FFFF, 0, 0, SATA_IRQ },
+ /* CSME (HECI, IDE-R, Keyboard and Text redirection */
+ Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
+ Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
+ Package(){0x0016FFFF, 2, 0, IDER_IRQ },
+ Package(){0x0016FFFF, 3, 0, KT_IRQ },
+ Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
+ Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
+ /* SerialIo */
+ Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+ Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+ Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+ Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
+ /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
+ Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
+ Package(){0x0014FFFF, 1, 0, OTG_IRQ },
+ Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
+ Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
+ Package(){0x0014FFFF, 5, 0, SD_IRQ },
+ /* SerialIo */
+ Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
+ /* SA IGFX Device */
+ Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
+ /* SA Thermal Device */
+ Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
+ /* SA IPU Device */
+ Package(){0x0005FFFF, 0, 0, IPU_IRQ },
+ /* SA GNA Device */
+ Package(){0x0008FFFF, 0, 0, GNA_IRQ },
+})
+
+Name (PICN, Package () {
+ /* D31: cAVS, SMBus, GbE, Northpeak */
+ Package () { 0x001FFFFF, 3, 0, 11 },
+ Package () { 0x001FFFFF, 4, 0, 10 },
+ Package () { 0x001FFFFF, 6, 0, 11 },
+ Package () { 0x001FFFFF, 7, 0, 11 },
+ /* D30: SerialIo */
+ Package () {0x001EFFFF, 0, 0, 11 },
+ Package () {0x001EFFFF, 1, 0, 10 },
+ Package () {0x001EFFFF, 2, 0, 11 },
+ Package () {0x001EFFFF, 3, 0, 11 },
+ /* D28: PCI Express Port 1-8 */
+ Package () { 0x001CFFFF, 0, 0, 11 },
+ Package () { 0x001CFFFF, 1, 0, 10 },
+ Package () { 0x001CFFFF, 2, 0, 11 },
+ Package () { 0x001CFFFF, 3, 0, 11 },
+ Package () { 0x001CFFFF, 4, 0, 11 },
+ Package () { 0x001CFFFF, 5, 0, 10 },
+ Package () { 0x001CFFFF, 6, 0, 11 },
+ Package () { 0x001CFFFF, 7, 0, 11 },
+ /* D26: eMMC */
+ Package(){0x001AFFFF, 0, 0, 11 },
+ /* D25: SerialIo */
+ Package () {0x0019FFFF, 0, 0, 11 },
+ Package () {0x0019FFFF, 1, 0, 10 },
+ Package () {0x0019FFFF, 2, 0, 11 },
+ /* D23: SATA controller */
+ Package () { 0x0017FFFF, 0, 0, 11 },
+ /* D22: CSME (HECI, IDE-R, KT redirection */
+ Package () { 0x0016FFFF, 0, 0, 11 },
+ Package () { 0x0016FFFF, 1, 0, 10 },
+ Package () { 0x0016FFFF, 2, 0, 11 },
+ Package () { 0x0016FFFF, 3, 0, 11 },
+ Package () { 0x0016FFFF, 4, 0, 11 },
+ Package () { 0x0016FFFF, 5, 0, 11 },
+ /* D21: SerialIo */
+ Package () {0x0015FFFF, 0, 0, 11 },
+ Package () {0x0015FFFF, 1, 0, 10 },
+ Package () {0x0015FFFF, 2, 0, 11 },
+ Package () {0x0015FFFF, 3, 0, 11 },
+ /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
+ Package () { 0x0014FFFF, 0, 0, 11 },
+ Package () { 0x0014FFFF, 1, 0, 10 },
+ Package () { 0x0014FFFF, 2, 0, 11 },
+ Package () { 0x0014FFFF, 3, 0, 11 },
+ Package () { 0x0014FFFF, 5, 0, 11 },
+ /* D18: SerialIo */
+ Package () {0x0012FFFF, 6, 0, 11 },
+ /* SA IGFX Device */
+ Package () {0x0002FFFF, 0, 0, 11 },
+ /* SA Thermal Device */
+ Package () { 0x0004FFFF, 0, 0, 11 },
+ /* SA IPU Device */
+ Package () { 0x0005FFFF, 0, 0, 11 },
+ /* SA GNA Device */
+ Package () { 0x0008FFFF, 0, 0, 11 },
+})
+
+Method (_PRT)
+{
+ If (PICM) {
+ Return (^PICP)
+ } Else {
+ Return (^PICN)
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl
new file mode 100644
index 0000000000..7f632ba32e
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/irq.h>
+
+Name (PICP, Package () {
+ /* D31:HSA, SMBUS, TraceHUB */
+ Package(){0x001FFFFF, 3, 0, HDA_IRQ },
+ Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
+ Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
+ /* D30: UART0, UART1, SPI0, SPI1 */
+ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+ Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
+ Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
+ Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
+ /* D29: RP9 ~ RP12 */
+ Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
+ Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
+ Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
+ Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
+ /* D28: RP1 ~ RP8 */
+ Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
+ Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
+ Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
+ Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
+ Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
+ Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
+ Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
+ Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
+ /* D25: I2C4, I2C5, UART2 */
+ Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
+ Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+ Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
+ /* D23: SATA */
+ Package(){0x0017FFFF, 0, 0, SATA_IRQ },
+ /* D22: CSME */
+ Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
+ Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
+ Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
+ Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
+ /* D21: I2C0 ~ I2C3 */
+ Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+ Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+ Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+ Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
+ /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
+ Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
+ Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
+ Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
+ /* D19: SPI3 */
+ Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
+ /* D18: ISH, SPI2 */
+ Package(){0x0012FFFF, 0, 0, ISH_IRQ },
+ Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
+ /* D16: CNVI_BT, TCH0, TCH1 */
+ Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
+ Package(){0x0010FFFF, 6, 0, THC0_IRQ },
+ Package(){0x0010FFFF, 7, 0, THC1_IRQ },
+ /* D13: xHCI, xDCI */
+ Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
+ Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
+ /* D8: GNA */
+ Package(){0x0008FFFF, 0, 0, GNA_IRQ },
+ /* D7: TBT PCIe */
+ Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
+ Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
+ Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
+ Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
+ /* D6: PEG60 */
+ Package(){0x0006FFFF, 0, 0, PEG_IRQ },
+ /* D5: IPU Device */
+ Package(){0x0005FFFF, 0, 0, IPU_IRQ },
+ /* D4: Thermal Device */
+ Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
+ /* D2: IGFX */
+ Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
+})
+
+Name (PICN, Package () {
+ /* D31:HSA, SMBUS, TraceHUB*/
+ Package () { 0x001FFFFF, 3, 0, 11 },
+ Package () { 0x001FFFFF, 4, 0, 11 },
+ Package () { 0x001FFFFF, 7, 0, 11 },
+ /* D30: UART0, UART1, SPI0, SPI1 */
+ Package () { 0x001EFFFF, 0, 0, 11 },
+ Package () { 0x001EFFFF, 1, 0, 10 },
+ Package () { 0x001EFFFF, 2, 0, 11 },
+ Package () { 0x001EFFFF, 3, 0, 11 },
+ /* D29: RP9 ~ RP12 */
+ Package () { 0x001DFFFF, 0, 0, 11 },
+ Package () { 0x001DFFFF, 1, 0, 10 },
+ Package () { 0x001DFFFF, 2, 0, 11 },
+ Package () { 0x001DFFFF, 3, 0, 11 },
+ /* D28: RP1 ~ RP8 */
+ Package () { 0x001CFFFF, 0, 0, 11 },
+ Package () { 0x001CFFFF, 1, 0, 10 },
+ Package () { 0x001CFFFF, 2, 0, 11 },
+ Package () { 0x001CFFFF, 3, 0, 11 },
+ Package () { 0x001CFFFF, 4, 0, 11 },
+ Package () { 0x001CFFFF, 5, 0, 10 },
+ Package () { 0x001CFFFF, 6, 0, 11 },
+ Package () { 0x001CFFFF, 7, 0, 11 },
+ /* D25: I2C4, I2C5, UART2 */
+ Package(){0x0019FFFF, 0, 0, 11 },
+ Package(){0x0019FFFF, 1, 0, 10 },
+ Package(){0x0019FFFF, 2, 0, 11 },
+ /* D23: SATA */
+ Package () { 0x0017FFFF, 0, 0, 11 },
+ /* D22: CSME */
+ Package(){0x0016FFFF, 0, 0, 11 },
+ Package(){0x0016FFFF, 1, 0, 10 },
+ Package(){0x0016FFFF, 4, 0, 11 },
+ Package(){0x0016FFFF, 5, 0, 11 },
+ /* D21: I2C0 ~ I2C3 */
+ Package(){0x0015FFFF, 0, 0, 11 },
+ Package(){0x0015FFFF, 1, 0, 10 },
+ Package(){0x0015FFFF, 2, 0, 11 },
+ Package(){0x0015FFFF, 3, 0, 11 },
+ /* D19: SPI3 */
+ Package(){0x0013FFFF, 0, 0, 11 },
+ /* D18: ISH, SPI2 */
+ Package(){0x0012FFFF, 0, 0, 11 },
+ Package(){0x0012FFFF, 6, 0, 11 },,
+ /* D16: CNVI_BT, TCH0, TCH1 */
+ Package(){0x0010FFFF, 2, 0, 11 },
+ Package(){0x0010FFFF, 6, 0, 11 },
+ Package(){0x0010FFFF, 7, 0, 10 },
+ /* D13: xHCI, xDCI */
+ Package(){0x000DFFFF, 0, 0, 11 },
+ Package(){0x000DFFFF, 1, 0, 10 },
+ /* D8: GNA */
+ Package(){0x0008FFFF, 0, 0, 11 },
+ /* D7: TBT PCIe */
+ Package(){0x0007FFFF, 0, 0, 11 },
+ Package(){0x0007FFFF, 1, 0, 10 },
+ Package(){0x0007FFFF, 2, 0, 11 },
+ Package(){0x0007FFFF, 3, 0, 11 },
+ /* D6: PEG60 */
+ Package(){0x0006FFFF, 0, 0, 11 },
+ /* D5: IPU Device */
+ Package(){0x0005FFFF, 0, 0, 11 },
+ /* D4: Thermal Device */
+ Package(){0x0004FFFF, 0, 0, 11 },
+ /* D2: IGFX */
+ Package(){0x0002FFFF, 0, 0, 11 },
+})
+
+Method (_PRT)
+{
+ If (PICM) {
+ Return (^PICP)
+ } Else {
+ Return (^PICN)
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/pcie.asl b/src/soc/intel/jasperlake/acpi/pcie.asl
new file mode 100644
index 0000000000..53ae316413
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pcie.asl
@@ -0,0 +1,313 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel PCH PCIe support */
+
+Method (IRQM, 1, Serialized) {
+
+ /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
+ Name (IQAA, Package () {
+ Package () { 0x0000ffff, 0, 0, 16 },
+ Package () { 0x0000ffff, 1, 0, 17 },
+ Package () { 0x0000ffff, 2, 0, 18 },
+ Package () { 0x0000ffff, 3, 0, 19 } })
+ Name (IQAP, Package () {
+ Package () { 0x0000ffff, 0, 0, 11 },
+ Package () { 0x0000ffff, 1, 0, 10 },
+ Package () { 0x0000ffff, 2, 0, 11 },
+ Package () { 0x0000ffff, 3, 0, 11 } })
+
+ /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
+ Name (IQBA, Package () {
+ Package () { 0x0000ffff, 0, 0, 17 },
+ Package () { 0x0000ffff, 1, 0, 18 },
+ Package () { 0x0000ffff, 2, 0, 19 },
+ Package () { 0x0000ffff, 3, 0, 16 } })
+ Name (IQBP, Package () {
+ Package () { 0x0000ffff, 0, 0, 10 },
+ Package () { 0x0000ffff, 1, 0, 11 },
+ Package () { 0x0000ffff, 2, 0, 11 },
+ Package () { 0x0000ffff, 3, 0, 11 } })
+
+ /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
+ Name (IQCA, Package () {
+ Package () { 0x0000ffff, 0, 0, 18 },
+ Package () { 0x0000ffff, 1, 0, 19 },
+ Package () { 0x0000ffff, 2, 0, 16 },
+ Package () { 0x0000ffff, 3, 0, 17 } })
+ Name (IQCP, Package () {
+ Package () { 0x0000ffff, 0, 0, 11 },
+ Package () { 0x0000ffff, 1, 0, 11 },
+ Package () { 0x0000ffff, 2, 0, 11 },
+ Package () { 0x0000ffff, 3, 0, 10 } })
+
+ /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
+ Name (IQDA, Package () {
+ Package () { 0x0000ffff, 0, 0, 19 },
+ Package () { 0x0000ffff, 1, 0, 16 },
+ Package () { 0x0000ffff, 2, 0, 17 },
+ Package () { 0x0000ffff, 3, 0, 18 } })
+ Name (IQDP, Package () {
+ Package () { 0x0000ffff, 0, 0, 11 },
+ Package () { 0x0000ffff, 1, 0, 11 },
+ Package () { 0x0000ffff, 2, 0, 10 },
+ Package () { 0x0000ffff, 3, 0, 11 } })
+
+ Switch (ToInteger (Arg0))
+ {
+ Case (Package () { 1, 5, 9, 13 }) {
+ If (PICM) {
+ Return (IQAA)
+ } Else {
+ Return (IQAP)
+ }
+ }
+
+ Case (Package () { 2, 6, 10, 14 }) {
+ If (PICM) {
+ Return (IQBA)
+ } Else {
+ Return (IQBP)
+ }
+ }
+
+ Case (Package () { 3, 7, 11, 15 }) {
+ If (PICM) {
+ Return (IQCA)
+ } Else {
+ Return (IQCP)
+ }
+ }
+
+ Case (Package () { 4, 8, 12, 16 }) {
+ If (PICM) {
+ Return (IQDA)
+ } Else {
+ Return (IQDP)
+ }
+ }
+
+ Default {
+ If (PICM) {
+ Return (IQDA)
+ } Else {
+ Return (IQDP)
+ }
+ }
+ }
+}
+
+Device (RP01)
+{
+ Name (_ADR, 0x001C0000)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP02)
+{
+ Name (_ADR, 0x001C0001)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP03)
+{
+ Name (_ADR, 0x001C0002)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP04)
+{
+ Name (_ADR, 0x001C0003)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP05)
+{
+ Name (_ADR, 0x001C0004)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP06)
+{
+ Name (_ADR, 0x001C0005)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP07)
+{
+ Name (_ADR, 0x001C0006)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP08)
+{
+ Name (_ADR, 0x001C0007)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP09)
+{
+ Name (_ADR, 0x001D0000)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP10)
+{
+ Name (_ADR, 0x001D0001)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP11)
+{
+ Name (_ADR, 0x001D0002)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP12)
+{
+ Name (_ADR, 0x001D0003)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/platform.asl b/src/soc/intel/jasperlake/acpi/platform.asl
new file mode 100644
index 0000000000..682a7b93d8
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/platform.asl
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+/* Generic indicator for sleep state */
+#include <soc/intel/common/acpi/platform.asl>
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method (_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice. */
+ Store (Arg0, PICM)
+}
diff --git a/src/soc/intel/jasperlake/acpi/pmc.asl b/src/soc/intel/jasperlake/acpi/pmc.asl
new file mode 100644
index 0000000000..6dd2d35354
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/pmc.asl
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+Scope (\_SB.PCI0) {
+
+ Device (PMC)
+ {
+ Name (_HID, "INTC1026")
+ Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
+ /*
+ * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF.
+ * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR.
+ */
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000)
+ })
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl
new file mode 100644
index 0000000000..83da7e0f06
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/scs.asl
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/pcr_ids.h>
+
+Scope (\_SB.PCI0) {
+
+ /*
+ * Clear register 0x1C20/0x4820
+ * Arg0 - PCR Port ID
+ */
+ Method(SCSC, 1, Serialized)
+ {
+ PCRA (Arg0, 0x1C20, 0x0)
+ PCRA (Arg0, 0x4820, 0x0)
+ }
+
+ /* EMMC */
+ Device(PEMC) {
+ Name(_ADR, 0x001A0000)
+ Name (_DDN, "eMMC Controller")
+ Name (TEMP, 0)
+
+ OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
+ Field(SCSR, WordAcc, NoLock, Preserve) {
+ Offset (0x84), /* PMECTRLSTATUS */
+ PMCR, 16,
+ Offset (0xA2), /* PG_CONFIG */
+ , 2,
+ PGEN, 1, /* PG_ENABLE */
+ }
+
+ Method(_INI) {
+ /* Clear register 0x1C20/0x4820 */
+ SCSC (PID_EMMC)
+ }
+
+ Method(_PS0, 0, Serialized) {
+ Stall (50) // Sleep 50 us
+
+ Store(0, PGEN) // Disable PG
+
+ /* Clear register 0x1C20/0x4820 */
+ SCSC (PID_EMMC)
+
+ /* Set Power State to D0 */
+ And (PMCR, 0xFFFC, PMCR)
+ Store (PMCR, TEMP)
+ }
+
+ Method(_PS3, 0, Serialized) {
+ Store(1, PGEN) // Enable PG
+
+ /* Set Power State to D3 */
+ Or (PMCR, 0x0003, PMCR)
+ Store (PMCR, TEMP)
+ }
+
+ Device (CARD)
+ {
+ Name (_ADR, 0x00000008)
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (0)
+ }
+ }
+ }
+
+ /* SD CARD */
+ Device (SDXC)
+ {
+ Name (_ADR, 0x00140005)
+ Name (_DDN, "SD Controller")
+ Name (TEMP, 0)
+
+ OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
+ Field (SDPC, WordAcc, NoLock, Preserve)
+ {
+ Offset (0x84), /* PMECTRLSTATUS */
+ PMCR, 16,
+ Offset (0xA2), /* PG_CONFIG */
+ , 2,
+ PGEN, 1, /* PG_ENABLE */
+ }
+
+ Method(_INI)
+ {
+ /* Clear register 0x1C20/0x4820 */
+ SCSC (PID_SDX)
+ }
+
+ Method (_PS0, 0, Serialized)
+ {
+ Store (0, PGEN) /* Disable PG */
+
+ /* Clear register 0x1C20/0x4820 */
+ SCSC (PID_SDX)
+
+ /* Set Power State to D0 */
+ And (PMCR, 0xFFFC, PMCR)
+ Store (PMCR, TEMP)
+ }
+
+ Method (_PS3, 0, Serialized)
+ {
+ Store (1, PGEN) /* Enable PG */
+
+ /* Set Power State to D3 */
+ Or (PMCR, 0x0003, PMCR)
+ Store (PMCR, TEMP)
+ }
+
+ Device (CARD)
+ {
+ Name (_ADR, 0x00000008)
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (1)
+ }
+ }
+ } /* Device (SDXC) */
+}
diff --git a/src/soc/intel/jasperlake/acpi/serialio.asl b/src/soc/intel/jasperlake/acpi/serialio.asl
new file mode 100644
index 0000000000..6fd135b437
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/serialio.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Serial IO Devices */
+
+Device (I2C0)
+{
+ Name (_ADR, 0x00150000)
+ Name (_DDN, "Serial IO I2C Controller 0")
+}
+
+Device (I2C1)
+{
+ Name (_ADR, 0x00150001)
+ Name (_DDN, "Serial IO I2C Controller 1")
+}
+
+Device (I2C2)
+{
+ Name (_ADR, 0x00150002)
+ Name (_DDN, "Serial IO I2C Controller 2")
+}
+
+Device (I2C3)
+{
+ Name (_ADR, 0x00150003)
+ Name (_DDN, "Serial IO I2C Controller 3")
+}
+
+Device (I2C4)
+{
+ Name (_ADR, 0x00190000)
+ Name (_DDN, "Serial IO I2C Controller 4")
+}
+
+Device (I2C5)
+{
+ Name (_ADR, 0x00190001)
+ Name (_DDN, "Serial IO I2C Controller 5")
+}
+
+Device (SPI0)
+{
+ Name (_ADR, 0x001e0002)
+ Name (_DDN, "Serial IO SPI Controller 0")
+}
+
+Device (SPI1)
+{
+ Name (_ADR, 0x001e0003)
+ Name (_DDN, "Serial IO SPI Controller 1")
+}
+
+Device (SPI2)
+{
+ Name (_ADR, 0x00120006)
+ Name (_DDN, "Serial IO SPI Controller 2")
+}
+
+Device (SPI3)
+{
+ Name (_ADR, 0x00130000)
+ Name (_DDN, "Serial IO SPI Controller 3")
+}
+
+Device (UAR0)
+{
+ Name (_ADR, 0x001e0000)
+ Name (_DDN, "Serial IO UART Controller 0")
+}
+
+Device (UAR1)
+{
+ Name (_ADR, 0x001e0001)
+ Name (_DDN, "Serial IO UART Controller 1")
+}
+
+Device (UAR2)
+{
+ Name (_ADR, 0x00190002)
+ Name (_DDN, "Serial IO UART Controller 2")
+}
diff --git a/src/soc/intel/jasperlake/acpi/smbus.asl b/src/soc/intel/jasperlake/acpi/smbus.asl
new file mode 100644
index 0000000000..f273e3669d
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/smbus.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel SMBus Controller 0:1f.4 */
+
+Device (SBUS)
+{
+ Name (_ADR, 0x001f0004)
+}
diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl
new file mode 100644
index 0000000000..6329340392
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/southbridge.asl
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/itss.h>
+#include <intelblocks/pcr.h>
+#include <soc/itss.h>
+#include <soc/pcr_ids.h>
+
+/* PCI IRQ assignment */
+#include "pci_irqs.asl"
+
+/* PCR access */
+#include <soc/intel/common/acpi/pcr.asl>
+
+/* PCH clock */
+#include "camera_clock_ctl.asl"
+
+/* GPIO controller */
+#include "gpio.asl"
+
+/* ESPI 0:1f.0 */
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
+
+/* PCH HDA */
+#include "pch_hda.asl"
+
+/* PCIE Ports */
+#include "pcie.asl"
+
+/* pmc 0:1f.2 */
+#include "pmc.asl"
+
+/* Serial IO */
+#include "serialio.asl"
+
+/* SMBus 0:1f.4 */
+#include "smbus.asl"
+
+/* ISH 0:12.0 */
+#include "ish.asl"
+
+/* USB XHCI 0:14.0 */
+#include "xhci.asl"
+
+/* PCI _OSC */
+#include <soc/intel/common/acpi/pci_osc.asl>
+
+/* PMC Core*/
+#include <soc/intel/common/block/acpi/acpi/pmc.asl>
diff --git a/src/soc/intel/jasperlake/acpi/xhci.asl b/src/soc/intel/jasperlake/acpi/xhci.asl
new file mode 100644
index 0000000000..9baf67ac5a
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/xhci.asl
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
+ #include "xhci_tgl.asl"
+#else
+ #include "xhci_jsl.asl"
+#endif
diff --git a/src/soc/intel/jasperlake/acpi/xhci_jsl.asl b/src/soc/intel/jasperlake/acpi/xhci_jsl.asl
new file mode 100644
index 0000000000..41be89ace1
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/xhci_jsl.asl
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpe.h>
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+ Name (_ADR, 0x00140000)
+
+ Name (_PRW, Package () { GPE0_PME_B0, 3 })
+
+ Name (_S3D, 3) /* D3 supported in S3 */
+ Name (_S0W, 3) /* D3 can wake device in S0 */
+ Name (_S3W, 3) /* D3 can wake system from S3 */
+
+ Method (_PS0, 0, Serialized)
+ {
+
+ }
+
+ Method (_PS3, 0, Serialized)
+ {
+
+ }
+
+ /* Root Hub for Jasperlake PCH */
+ Device (RHUB)
+ {
+ Name (_ADR, Zero)
+
+ /* USB2 */
+ Device (HS01) { Name (_ADR, 1) }
+ Device (HS02) { Name (_ADR, 2) }
+ Device (HS03) { Name (_ADR, 3) }
+ Device (HS04) { Name (_ADR, 4) }
+ Device (HS05) { Name (_ADR, 5) }
+ Device (HS06) { Name (_ADR, 6) }
+ Device (HS07) { Name (_ADR, 7) }
+ Device (HS08) { Name (_ADR, 8) }
+
+ /* USB3 */
+ Device (SS01) { Name (_ADR, 9) }
+ Device (SS02) { Name (_ADR, 10) }
+ Device (SS03) { Name (_ADR, 11) }
+ Device (SS04) { Name (_ADR, 12) }
+ Device (SS05) { Name (_ADR, 13) }
+ Device (SS06) { Name (_ADR, 14) }
+ }
+}
diff --git a/src/soc/intel/jasperlake/acpi/xhci_tgl.asl b/src/soc/intel/jasperlake/acpi/xhci_tgl.asl
new file mode 100644
index 0000000000..b97f52052b
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi/xhci_tgl.asl
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpe.h>
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+ Name (_ADR, 0x00140000)
+
+ Name (_PRW, Package () { GPE0_PME_B0, 3 })
+
+ Name (_S3D, 3) /* D3 supported in S3 */
+ Name (_S0W, 3) /* D3 can wake device in S0 */
+ Name (_S3W, 3) /* D3 can wake system from S3 */
+
+ Method (_PS0, 0, Serialized)
+ {
+
+ }
+
+ Method (_PS3, 0, Serialized)
+ {
+
+ }
+
+ /* Root Hub for Tigerlake-LP PCH */
+ Device (RHUB)
+ {
+ Name (_ADR, Zero)
+
+ /* USB2 */
+ Device (HS01) { Name (_ADR, 1) }
+ Device (HS02) { Name (_ADR, 2) }
+ Device (HS03) { Name (_ADR, 3) }
+ Device (HS04) { Name (_ADR, 4) }
+ Device (HS05) { Name (_ADR, 5) }
+ Device (HS06) { Name (_ADR, 6) }
+ Device (HS07) { Name (_ADR, 7) }
+ Device (HS08) { Name (_ADR, 8) }
+ Device (HS09) { Name (_ADR, 9) }
+ Device (HS10) { Name (_ADR, 10) }
+
+ /* USB3 */
+ Device (SS01) { Name (_ADR, 13) }
+ Device (SS02) { Name (_ADR, 14) }
+ Device (SS03) { Name (_ADR, 15) }
+ Device (SS04) { Name (_ADR, 16) }
+ }
+}
diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c
new file mode 100644
index 0000000000..1abca127a3
--- /dev/null
+++ b/src/soc/intel/jasperlake/bootblock/bootblock.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/systemagent.h>
+#include <intelblocks/uart.h>
+#include <soc/bootblock.h>
+#include <soc/iomap.h>
+#include <soc/pch.h>
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+ /* Call lib/bootblock.c main */
+ bootblock_main_with_basetime(base_timestamp);
+}
+
+void bootblock_soc_early_init(void)
+{
+ bootblock_systemagent_early_init();
+ bootblock_pch_early_init();
+ bootblock_cpu_init();
+ pch_early_iorange_init();
+ if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+ uart_bootblock_init();
+}
+
+void bootblock_soc_init(void)
+{
+ report_platform_info();
+ pch_init();
+}
diff --git a/src/soc/intel/jasperlake/bootblock/cpu.c b/src/soc/intel/jasperlake/bootblock/cpu.c
new file mode 100644
index 0000000000..dddf24352d
--- /dev/null
+++ b/src/soc/intel/jasperlake/bootblock/cpu.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 6
+ */
+
+#include <intelblocks/fast_spi.h>
+#include <soc/bootblock.h>
+
+void bootblock_cpu_init(void)
+{
+ /*
+ * Tigerlake platform doesn't support booting from any other media
+ * (like eMMC on APL/GLK platform) than only booting from SPI device
+ * and on IA platform SPI is memory mapped hence enabling temporarily
+ * cacheing on memory-mapped spi boot media.
+ *
+ * This assumption will not hold good for APL/GLK platform where boot
+ * from eMMC is also possible options.
+ */
+ fast_spi_cache_bios_region();
+}
diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c
new file mode 100644
index 0000000000..b0646018c6
--- /dev/null
+++ b/src/soc/intel/jasperlake/bootblock/pch.c
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 2, 3, 4, 27, 28
+ */
+
+#include <console/console.h>
+#include <console/post_codes.h>
+#include <device/mmio.h>
+#include <device/device.h>
+#include <device/pci_ops.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/p2sb.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/rtc.h>
+#include <soc/bootblock.h>
+#include <soc/espi.h>
+#include <soc/iomap.h>
+#include <soc/p2sb.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x1100
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0xA00
+#define PCR_PSFX_TO_SHDW_BAR0 0
+#define PCR_PSFX_TO_SHDW_BAR1 0x4
+#define PCR_PSFX_TO_SHDW_BAR2 0x8
+#define PCR_PSFX_TO_SHDW_BAR3 0xC
+#define PCR_PSFX_TO_SHDW_BAR4 0x10
+#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
+#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
+
+#define PCR_DMI_DMICTL 0x2234
+#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
+
+#define PCR_DMI_ACPIBA 0x27B4
+#define PCR_DMI_ACPIBDID 0x27B8
+#define PCR_DMI_PMBASEA 0x27AC
+#define PCR_DMI_PMBASEC 0x27B0
+
+#define PCR_DMI_LPCIOD 0x2770
+#define PCR_DMI_LPCIOE 0x2774
+
+static uint32_t get_pmc_reg_base(void)
+{
+ uint8_t pch_series;
+
+ pch_series = get_pch_series();
+
+ if (pch_series == PCH_TGP)
+ return PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP;
+ else if (pch_series == PCH_JSP)
+ return PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP;
+ else
+ return 0;
+}
+
+static void soc_config_pwrmbase(void)
+{
+ uint32_t reg32;
+
+ /*
+ * Assign Resources to PWRMBASE
+ * Clear BIT 1-2 Command Register
+ */
+ reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
+ reg32 &= ~(PCI_COMMAND_MEMORY);
+ pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+
+ /* Program PWRM Base */
+ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
+
+ /* Enable Bus Master and MMIO Space */
+ reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MEMORY;
+ pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+
+ /* Enable PWRM in PMC */
+ reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
+ write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
+}
+
+void bootblock_pch_early_init(void)
+{
+ fast_spi_early_init(SPI_BASE_ADDRESS);
+ gspi_early_bar_init();
+ p2sb_enable_bar();
+ p2sb_configure_hpet();
+
+ /*
+ * Enabling PWRM Base for accessing
+ * Global Reset Cause Register.
+ */
+ soc_config_pwrmbase();
+}
+
+static void soc_config_acpibase(void)
+{
+ uint32_t pmc_reg_value;
+ uint32_t pmc_base_reg;
+
+ pmc_base_reg = get_pmc_reg_base();
+ if (!pmc_base_reg)
+ die_with_post_code(POST_HW_INIT_FAILURE, "Invalid PMC base address\n");
+
+ pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
+
+ if (pmc_reg_value != 0xffffffff) {
+ /* Disable Io Space before changing the address */
+ pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
+ ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
+ /* Program ABASE in PSF3 PMC space BAR4*/
+ pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
+ ACPI_BASE_ADDRESS);
+ /* Enable IO Space */
+ pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
+ ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
+ }
+}
+
+static int pch_check_decode_enable(void)
+{
+ uint32_t dmi_control;
+
+ /*
+ * This cycle decoding is only allowed to set when
+ * DMICTL.SRLOCK is 0.
+ */
+ dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
+ if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
+ return -1;
+ return 0;
+}
+
+void pch_early_iorange_init(void)
+{
+ uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+ LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
+
+ /* IO Decode Range */
+ if (CONFIG(DRIVERS_UART_8250IO))
+ lpc_io_setup_comm_a_b();
+
+ /* IO Decode Enable */
+ if (pch_check_decode_enable() == 0) {
+ io_enables = lpc_enable_fixed_io_ranges(io_enables);
+ /*
+ * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
+ * value programmed in ESPI PCI offset 82h.
+ */
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+ /*
+ * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
+ * value programmed in LPC PCI offset 80h.
+ */
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
+ }
+
+ /* Program generic IO Decode Range */
+ pch_enable_lpc();
+}
+
+void pch_init(void)
+{
+ /*
+ * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
+ * GPE0_STS, GPE0_EN registers.
+ */
+ soc_config_acpibase();
+
+ /* Set up GPE configuration */
+ pmc_gpe_init();
+
+ enable_rtc_upper_bank();
+}
diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c
new file mode 100644
index 0000000000..d7b2e0db32
--- /dev/null
+++ b/src/soc/intel/jasperlake/bootblock/report_platform.c
@@ -0,0 +1,246 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Platform Stepping and IDs
+ * Document number: 605534
+ * Chapter number: 2, 4, 5, 6
+ */
+
+#include <arch/cpu.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelblocks/mp_init.h>
+#include <soc/bootblock.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <string.h>
+
+#define BIOS_SIGN_ID 0x8B
+
+static struct {
+ u32 cpuid;
+ const char *name;
+} cpu_table[] = {
+ { CPUID_TIGERLAKE_A0, "Tigerlake A0" },
+ { CPUID_JASPERLAKE_A0, "Jasperlake A0" },
+};
+
+static struct {
+ u16 mchid;
+ const char *name;
+} mch_table[] = {
+ { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" },
+ { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" },
+ { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" },
+ { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" },
+ { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake-1" },
+ { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" },
+ { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" },
+};
+
+static struct {
+ u16 espiid;
+ const char *name;
+} pch_table[] = {
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_0, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, "Tigerlake-U Super SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, "Tigerlake-U Premium SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI, "Tigerlake-U Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_1, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_2, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI, "Tigerlake-Y Super SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI, "Tigerlake-Y Premium SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_3, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_4, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_5, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_6, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_7, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_8, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_9, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_10, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_11, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_12, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_13, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_14, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_15, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_16, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_17, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_18, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_19, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_20, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_21, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_22, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_23, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" },
+ { PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, "Jasperlake Super" },
+ { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" },
+ { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" },
+ { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" },
+ { PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" },
+ { PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" },
+};
+
+static struct {
+ u16 igdid;
+ const char *name;
+} igd_table[] = {
+ { PCI_DEVICE_ID_INTEL_TGL_GT0, "Tigerlake U GT0" },
+ { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" },
+ { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" },
+ { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" },
+ { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" },
+ { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" },
+ { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" },
+ { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" },
+ { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" },
+ { PCI_DEVICE_ID_INTEL_EHL_GT2_2, "Elkhartlake GT2 2" },
+ { PCI_DEVICE_ID_INTEL_EHL_GT1_3, "Elkhartlake GT1 3" },
+ { PCI_DEVICE_ID_INTEL_EHL_GT2_3, "Elkhartlake GT2 3" },
+};
+
+static inline uint8_t get_dev_revision(pci_devfn_t dev)
+{
+ return pci_read_config8(dev, PCI_REVISION_ID);
+}
+
+static inline uint16_t get_dev_id(pci_devfn_t dev)
+{
+ return pci_read_config16(dev, PCI_DEVICE_ID);
+}
+
+static void report_cpu_info(void)
+{
+ struct cpuid_result cpuidr;
+ u32 i, index, cpu_id, cpu_feature_flag;
+ const char cpu_not_found[] = "Platform info not available";
+ const char *cpu_name = cpu_not_found; /* 48 bytes are reported */
+ int vt, txt, aes;
+ msr_t microcode_ver;
+ static const char *const mode[] = {"NOT ", ""};
+ const char *cpu_type = "Unknown";
+ u32 p[13];
+
+ index = 0x80000000;
+ cpuidr = cpuid(index);
+ if (cpuidr.eax >= 0x80000004) {
+ int j = 0;
+
+ for (i = 2; i <= 4; i++) {
+ cpuidr = cpuid(index + i);
+ p[j++] = cpuidr.eax;
+ p[j++] = cpuidr.ebx;
+ p[j++] = cpuidr.ecx;
+ p[j++] = cpuidr.edx;
+ }
+ p[12] = 0;
+ cpu_name = (char *)p;
+
+ /* Skip leading spaces in CPU name string */
+ while (cpu_name[0] == ' ' && strlen(cpu_name) > 0)
+ cpu_name++;
+ }
+
+ microcode_ver.lo = 0;
+ microcode_ver.hi = 0;
+ wrmsr(BIOS_SIGN_ID, microcode_ver);
+ cpu_id = cpu_get_cpuid();
+ microcode_ver = rdmsr(BIOS_SIGN_ID);
+
+ /* Look for string to match the name */
+ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
+ if (cpu_table[i].cpuid == cpu_id) {
+ cpu_type = cpu_table[i].name;
+ break;
+ }
+ }
+
+ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
+ printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
+ cpu_id, cpu_type, microcode_ver.hi);
+
+ cpu_feature_flag = cpu_get_feature_flags_ecx();
+ aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
+ txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
+ vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
+ printk(BIOS_DEBUG,
+ "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
+ mode[aes], mode[txt], mode[vt]);
+}
+
+static void report_mch_info(void)
+{
+ int i;
+ pci_devfn_t dev = SA_DEV_ROOT;
+ uint16_t mchid = get_dev_id(dev);
+ uint8_t mch_revision = get_dev_revision(dev);
+ const char *mch_type = "Unknown";
+
+ for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
+ if (mch_table[i].mchid == mchid) {
+ mch_type = mch_table[i].name;
+ break;
+ }
+ }
+
+ printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
+ mchid, mch_revision, mch_type);
+}
+
+static void report_pch_info(void)
+{
+ int i;
+ pci_devfn_t dev = PCH_DEV_ESPI;
+ uint16_t espiid = get_dev_id(dev);
+ const char *pch_type = "Unknown";
+
+ for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+ if (pch_table[i].espiid == espiid) {
+ pch_type = pch_table[i].name;
+ break;
+ }
+ }
+ printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
+ espiid, get_dev_revision(dev), pch_type);
+}
+
+static void report_igd_info(void)
+{
+ int i;
+ pci_devfn_t dev = SA_DEV_IGD;
+ uint16_t igdid = get_dev_id(dev);
+ const char *igd_type = "Unknown";
+
+ for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
+ if (igd_table[i].igdid == igdid) {
+ igd_type = igd_table[i].name;
+ break;
+ }
+ }
+ printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
+ igdid, get_dev_revision(dev), igd_type);
+}
+
+void report_platform_info(void)
+{
+ report_cpu_info();
+ report_mch_info();
+ report_pch_info();
+ report_igd_info();
+}
diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
new file mode 100644
index 0000000000..1c7078d6cf
--- /dev/null
+++ b/src/soc/intel/jasperlake/chip.c
@@ -0,0 +1,183 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <intelblocks/acpi.h>
+#include <intelblocks/cfg.h>
+#include <intelblocks/itss.h>
+#include <intelblocks/xdci.h>
+#include <romstage_handoff.h>
+#include <soc/intel/common/vbt.h>
+#include <soc/itss.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/soc_chip.h>
+
+#if CONFIG(HAVE_ACPI_TABLES)
+const char *soc_acpi_name(const struct device *dev)
+{
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ return "PCI0";
+
+ if (dev->path.type == DEVICE_PATH_USB) {
+ switch (dev->path.usb.port_type) {
+ case 0:
+ /* Root Hub */
+ return "RHUB";
+ case 2:
+ /* USB2 ports */
+ switch (dev->path.usb.port_id) {
+ case 0: return "HS01";
+ case 1: return "HS02";
+ case 2: return "HS03";
+ case 3: return "HS04";
+ case 4: return "HS05";
+ case 5: return "HS06";
+ case 6: return "HS07";
+ case 7: return "HS08";
+ case 8: return "HS09";
+ case 9: return "HS10";
+ }
+ break;
+ case 3:
+ /* USB3 ports */
+ switch (dev->path.usb.port_id) {
+ case 0: return "SS01";
+ case 1: return "SS02";
+ case 2: return "SS03";
+ case 3: return "SS04";
+ }
+ break;
+ }
+ return NULL;
+ }
+ if (dev->path.type != DEVICE_PATH_PCI)
+ return NULL;
+
+ switch (dev->path.pci.devfn) {
+ case SA_DEVFN_ROOT: return "MCHC";
+ case PCH_DEVFN_ISH: return "ISHB";
+ case PCH_DEVFN_XHCI: return "XHCI";
+ case PCH_DEVFN_I2C0: return "I2C0";
+ case PCH_DEVFN_I2C1: return "I2C1";
+ case PCH_DEVFN_I2C2: return "I2C2";
+ case PCH_DEVFN_I2C3: return "I2C3";
+ case PCH_DEVFN_I2C4: return "I2C4";
+ case PCH_DEVFN_I2C5: return "I2C5";
+ case PCH_DEVFN_SATA: return "SATA";
+ case PCH_DEVFN_PCIE1: return "RP01";
+ case PCH_DEVFN_PCIE2: return "RP02";
+ case PCH_DEVFN_PCIE3: return "RP03";
+ case PCH_DEVFN_PCIE4: return "RP04";
+ case PCH_DEVFN_PCIE5: return "RP05";
+ case PCH_DEVFN_PCIE6: return "RP06";
+ case PCH_DEVFN_PCIE7: return "RP07";
+ case PCH_DEVFN_PCIE8: return "RP08";
+ case PCH_DEVFN_PCIE9: return "RP09";
+ case PCH_DEVFN_PCIE10: return "RP10";
+ case PCH_DEVFN_PCIE11: return "RP11";
+ case PCH_DEVFN_PCIE12: return "RP12";
+ case PCH_DEVFN_UART0: return "UAR0";
+ case PCH_DEVFN_UART1: return "UAR1";
+ case PCH_DEVFN_UART2: return "UAR2";
+ case PCH_DEVFN_GSPI0: return "SPI0";
+ case PCH_DEVFN_GSPI1: return "SPI1";
+ case PCH_DEVFN_GSPI2: return "SPI2";
+ case PCH_DEVFN_GSPI3: return "SPI3";
+ /* Keeping ACPI device name coherent with ec.asl */
+ case PCH_DEVFN_ESPI: return "LPCB";
+ case PCH_DEVFN_HDA: return "HDAS";
+ case PCH_DEVFN_SMBUS: return "SBUS";
+ case PCH_DEVFN_GBE: return "GLAN";
+ }
+
+ return NULL;
+}
+#endif
+
+/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */
+static void soc_fill_gpio_pm_configuration(void)
+{
+ uint8_t value[TOTAL_GPIO_COMM];
+ const config_t *config = config_of_soc();
+
+ if (config->gpio_override_pm)
+ memcpy(value, config->gpio_pm, sizeof(uint8_t) *
+ TOTAL_GPIO_COMM);
+ else
+ memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ TOTAL_GPIO_COMM);
+
+ gpio_pm_configure(value, TOTAL_GPIO_COMM);
+}
+
+void soc_init_pre_device(void *chip_info)
+{
+ /* Snapshot the current GPIO IRQ polarities. FSP is setting a
+ * default policy that doesn't honor boards' requirements. */
+ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
+ /* Perform silicon specific init. */
+ fsp_silicon_init(romstage_handoff_is_resume());
+
+ /* Display FIRMWARE_VERSION_INFO_HOB */
+ fsp_display_fvi_version_hob();
+
+ /* Restore GPIO IRQ polarities back to previous settings. */
+ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
+ soc_fill_gpio_pm_configuration();
+}
+
+static void pci_domain_set_resources(struct device *dev)
+{
+ assign_resources(dev->link_list);
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = &pci_domain_read_resources,
+ .set_resources = &pci_domain_set_resources,
+ .scan_bus = &pci_domain_scan_bus,
+#if CONFIG(HAVE_ACPI_TABLES)
+ .acpi_name = &soc_acpi_name,
+#endif
+};
+
+static struct device_operations cpu_bus_ops = {
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = DEVICE_NOOP,
+#if CONFIG(HAVE_ACPI_TABLES)
+ .acpi_fill_ssdt_generator = generate_cpu_entries,
+#endif
+};
+
+static void soc_enable(struct device *dev)
+{
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ dev->ops = &pci_domain_ops;
+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
+ dev->ops = &cpu_bus_ops;
+}
+
+struct chip_operations soc_intel_tigerlake_ops = {
+ CHIP_NAME("Intel Tigerlake")
+ .enable_dev = &soc_enable,
+ .init = &soc_init_pre_device,
+};
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
new file mode 100644
index 0000000000..f82f13d45b
--- /dev/null
+++ b/src/soc/intel/jasperlake/chip.h
@@ -0,0 +1,299 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CHIP_H_
+#define _SOC_CHIP_H_
+
+#include <drivers/i2c/designware/dw_i2c.h>
+#include <intelblocks/cfg.h>
+#include <intelblocks/gpio.h>
+#include <intelblocks/gspi.h>
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+#include <soc/gpio_defs.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/serialio.h>
+#include <soc/usb.h>
+#include <stdint.h>
+
+#define MAX_HD_AUDIO_DMIC_LINKS 2
+#define MAX_HD_AUDIO_SNDW_LINKS 4
+#define MAX_HD_AUDIO_SSP_LINKS 6
+
+struct soc_intel_tigerlake_config {
+
+ /* Common struct containing soc config data required by common code */
+ struct soc_intel_common_config common_soc_config;
+
+ /* Gpio group routed to each dword of the GPE0 block. Values are
+ * of the form PMC_GPP_[A:U] or GPD. */
+ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
+ uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
+ uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
+
+ /* Generic IO decode ranges */
+ uint32_t gen1_dec;
+ uint32_t gen2_dec;
+ uint32_t gen3_dec;
+ uint32_t gen4_dec;
+
+ /* Enable S0iX support */
+ int s0ix_enable;
+ /* Enable DPTF support */
+ int dptf_enable;
+
+ /* Deep SX enable for both AC and DC */
+ int deep_s3_enable_ac;
+ int deep_s3_enable_dc;
+ int deep_s5_enable_ac;
+ int deep_s5_enable_dc;
+
+ /* Deep Sx Configuration
+ * DSX_EN_WAKE_PIN - Enable WAKE# pin
+ * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
+ * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
+ uint32_t deep_sx_config;
+
+ /* TCC activation offset */
+ uint32_t tcc_offset;
+
+ /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
+ * When enabled memory will be training at two different frequencies.
+ * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
+ * 4:FixedPoint3, 5:Enabled */
+ enum {
+ SaGv_Disabled,
+ SaGv_FixedPoint0,
+ SaGv_FixedPoint1,
+ SaGv_FixedPoint2,
+ SaGv_FixedPoint3,
+ SaGv_Enabled,
+ } SaGv;
+
+ /* Rank Margin Tool. 1:Enable, 0:Disable */
+ uint8_t RMT;
+
+ /* USB related */
+ struct usb2_port_config usb2_ports[16];
+ struct usb3_port_config usb3_ports[10];
+ /* Wake Enable Bitmap for USB2 ports */
+ uint16_t usb2_wake_enable_bitmap;
+ /* Wake Enable Bitmap for USB3 ports */
+ uint16_t usb3_wake_enable_bitmap;
+
+ /* SATA related */
+ uint8_t SataEnable;
+ uint8_t SataMode;
+ uint8_t SataSalpSupport;
+ uint8_t SataPortsEnable[8];
+ uint8_t SataPortsDevSlp[8];
+
+ /* Audio related */
+ uint8_t PchHdaDspEnable;
+ uint8_t PchHdaAudioLinkHdaEnable;
+ uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
+ uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
+ uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
+ uint8_t PchHdaIDispLinkTmode;
+ uint8_t PchHdaIDispLinkFrequency;
+ uint8_t PchHdaIDispCodecDisconnect;
+
+ /* PCIe Root Ports */
+ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
+ /* PCIe output clocks type to PCIe devices.
+ * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
+ * 0xFF: not used */
+ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
+ /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
+ * clksrc. */
+ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
+
+ /* PCIe RP L1 substate */
+ enum L1_substates_control {
+ L1_SS_FSP_DEFAULT,
+ L1_SS_DISABLED,
+ L1_SS_L1_1,
+ L1_SS_L1_2,
+ } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
+
+ /* SMBus */
+ uint8_t SmbusEnable;
+
+ /* eMMC and SD */
+ uint8_t ScsEmmcHs400Enabled;
+
+ /* Enable if SD Card Power Enable Signal is Active High */
+ uint8_t SdCardPowerEnableActiveHigh;
+
+ /* Integrated Sensor */
+ uint8_t PchIshEnable;
+
+ /* Heci related */
+ uint8_t Heci3Enabled;
+
+ /* Gfx related */
+ uint8_t IgdDvmt50PreAlloc;
+ uint8_t InternalGfx;
+ uint8_t SkipExtGfxScan;
+
+ uint32_t GraphicsConfigPtr;
+ uint8_t Device4Enable;
+
+ /* HeciEnabled decides the state of Heci1 at end of boot
+ * Setting to 0 (default) disables Heci1 and hides the device from OS */
+ uint8_t HeciEnabled;
+ /* PL2 Override value in Watts */
+ uint32_t tdp_pl2_override;
+ /* Intel Speed Shift Technology */
+ uint8_t speed_shift_enable;
+
+ /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
+ uint8_t eist_enable;
+
+ /* Enable C6 DRAM */
+ uint8_t enable_c6dram;
+ /*
+ * PRMRR size setting with below options
+ * Disable: 0x0
+ * 32MB: 0x2000000
+ * 64MB: 0x4000000
+ * 128 MB: 0x8000000
+ * 256 MB: 0x10000000
+ * 512 MB: 0x20000000
+ */
+ uint32_t PrmrrSize;
+ uint8_t PmTimerDisabled;
+ /*
+ * SerialIO device mode selection:
+ * PchSerialIoDisabled,
+ * PchSerialIoPci,
+ * PchSerialIoHidden,
+ * PchSerialIoLegacyUart,
+ * PchSerialIoSkipInit
+ */
+ uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
+ uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
+ /*
+ * GSPIn Default Chip Select Mode:
+ * 0:Hardware Mode,
+ * 1:Software Mode
+ */
+ uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ /*
+ * GSPIn Default Chip Select State:
+ * 0: Low,
+ * 1: High
+ */
+ uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+
+ /*
+ * TraceHubMode config
+ * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
+ */
+ uint8_t TraceHubMode;
+
+ /* Debug interface selection */
+ enum {
+ DEBUG_INTERFACE_RAM = (1 << 0),
+ DEBUG_INTERFACE_UART = (1 << 1),
+ DEBUG_INTERFACE_USB3 = (1 << 3),
+ DEBUG_INTERFACE_SERIAL_IO = (1 << 4),
+ DEBUG_INTERFACE_TRACEHUB = (1 << 5),
+ } debug_interface_flag;
+
+ /* GPIO SD card detect pin */
+ unsigned int sdcard_cd_gpio;
+
+ /* Enable Pch iSCLK */
+ uint8_t pch_isclk;
+
+ /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
+ enum {
+ FORCE_DISABLE,
+ FORCE_ENABLE,
+ } CnviBtAudioOffload;
+
+ /* Tcss */
+ uint8_t TcssXhciEn;
+ uint8_t TcssXdciEn;
+
+ /*
+ * Override GPIO PM configuration:
+ * 0: Use FSP default GPIO PM program,
+ * 1: coreboot to override GPIO PM program
+ */
+ uint8_t gpio_override_pm;
+
+ /*
+ * GPIO PM configuration: 0 to disable, 1 to enable power gating
+ * Bit 6-7: Reserved
+ * Bit 5: MISCCFG_GPSIDEDPCGEN
+ * Bit 4: MISCCFG_GPRCOMPCDLCGEN
+ * Bit 3: MISCCFG_GPRTCDLCGEN
+ * Bit 2: MISCCFG_GSXLCGEN
+ * Bit 1: MISCCFG_GPDPCGEN
+ * Bit 0: MISCCFG_GPDLCGEN
+ */
+ uint8_t gpio_pm[TOTAL_GPIO_COMM];
+
+ /* DP config */
+ /*
+ * Port config
+ * 0:Disabled, 1:eDP, 2:MIPI DSI
+ */
+ uint8_t DdiPortAConfig;
+ uint8_t DdiPortBConfig;
+
+ /* Enable(1)/Disable(0) HPD */
+ uint8_t DdiPortAHpd;
+ uint8_t DdiPortBHpd;
+ uint8_t DdiPortCHpd;
+ uint8_t DdiPort1Hpd;
+ uint8_t DdiPort2Hpd;
+ uint8_t DdiPort3Hpd;
+ uint8_t DdiPort4Hpd;
+
+ /* Enable(1)/Disable(0) DDC */
+ uint8_t DdiPortADdc;
+ uint8_t DdiPortBDdc;
+ uint8_t DdiPortCDdc;
+ uint8_t DdiPort1Ddc;
+ uint8_t DdiPort2Ddc;
+ uint8_t DdiPort3Ddc;
+ uint8_t DdiPort4Ddc;
+
+ /* Hybrid storage mode enable (1) / disable (0)
+ * This mode makes FSP detect Optane and NVME and set PCIe lane mode
+ * accordingly */
+ uint8_t HybridStorageMode;
+
+ /*
+ * Override CPU flex ratio value:
+ * CPU ratio value controls the maximum processor non-turbo ratio.
+ * Valid Range 0 to 63.
+ * In general descriptor provides option to set default cpu flex ratio.
+ * Default cpu flex ratio 0 ensures booting with non-turbo max frequency.
+ * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
+ * Only override CPU flex ratio to not boot with non-turbo max.
+ */
+ uint8_t cpu_ratio_override;
+
+};
+
+typedef struct soc_intel_tigerlake_config config_t;
+
+#endif
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
new file mode 100644
index 0000000000..dfbcd22b94
--- /dev/null
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -0,0 +1,267 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor CPU Datasheet
+ * Document number: 575683
+ * Chapter number: 15
+ */
+
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/turbo.h>
+#include <fsp/api.h>
+#include <intelblocks/cpulib.h>
+#include <intelblocks/mp_init.h>
+#include <intelblocks/msr.h>
+#include <romstage_handoff.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/soc_chip.h>
+
+static void soc_fsp_load(void)
+{
+ fsps_load(romstage_handoff_is_resume());
+}
+
+static void configure_isst(void)
+{
+ config_t *conf = config_of_soc();
+ msr_t msr;
+
+ if (conf->speed_shift_enable) {
+ /*
+ * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
+ * is supported or not. coreboot needs to configure MSR 0x1AA
+ * which is then reflected in the CPUID register.
+ */
+ msr = rdmsr(MSR_MISC_PWR_MGMT);
+ msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
+ msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
+ msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
+ wrmsr(MSR_MISC_PWR_MGMT, msr);
+ } else {
+ msr = rdmsr(MSR_MISC_PWR_MGMT);
+ msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
+ msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
+ msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
+ wrmsr(MSR_MISC_PWR_MGMT, msr);
+ }
+}
+
+static void configure_misc(void)
+{
+ msr_t msr;
+
+ config_t *conf = config_of_soc();
+
+ msr = rdmsr(IA32_MISC_ENABLE);
+ msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+
+ /* Set EIST status */
+ cpu_set_eist(conf->eist_enable);
+
+ /* Disable Thermal interrupts */
+ msr.lo = 0;
+ msr.hi = 0;
+ wrmsr(IA32_THERM_INTERRUPT, msr);
+
+ /* Enable package critical interrupt only */
+ msr.lo = 1 << 4;
+ msr.hi = 0;
+ wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
+
+ /* Enable PROCHOT */
+ msr = rdmsr(MSR_POWER_CTL);
+ msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/
+ msr.lo |= (1 << 23); /* Lock it */
+ wrmsr(MSR_POWER_CTL, msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(MSR_PIC_MSG_CONTROL);
+ msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
+ wrmsr(MSR_PIC_MSG_CONTROL, msr);
+}
+
+static void configure_dca_cap(void)
+{
+ uint32_t feature_flag;
+ msr_t msr;
+
+ /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+ feature_flag = cpu_get_feature_flags_ecx();
+ if (feature_flag & CPUID_DCA) {
+ msr = rdmsr(IA32_PLATFORM_DCA_CAP);
+ msr.lo |= 1;
+ wrmsr(IA32_PLATFORM_DCA_CAP, msr);
+ }
+}
+
+static void enable_pm_timer_emulation(void)
+{
+ /* ACPI PM timer emulation */
+ msr_t msr;
+ /*
+ * The derived frequency is calculated as follows:
+ * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer
+ * frequency is used.
+ */
+ msr.hi = (3579545ULL << 32) / CTC_FREQ;
+ /* Set PM1 timer IO port and enable */
+ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
+ EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
+ wrmsr(MSR_EMULATE_PM_TIMER, msr);
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+ msr_t msr;
+ int ecx;
+
+ /* Determine if energy efficient policy is supported. */
+ ecx = cpuid_ecx(0x6);
+ if (!(ecx & (1 << 3)))
+ return;
+
+ /* Energy Policy is bits 3:0 */
+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);
+ msr.lo &= ~0xf;
+ msr.lo |= policy & 0xf;
+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);
+}
+
+static void configure_c_states(void)
+{
+ msr_t msr;
+
+ /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
+
+ /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
+
+ /* C-state Interrupt Response Latency Control 3 - package C8 */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_32768_NS |
+ C_STATE_LATENCY_CONTROL_3_LIMIT;
+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
+
+ /* C-state Interrupt Response Latency Control 4 - package C9 */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_32768_NS |
+ C_STATE_LATENCY_CONTROL_4_LIMIT;
+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
+
+ /* C-state Interrupt Response Latency Control 5 - package C10 */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_32768_NS |
+ C_STATE_LATENCY_CONTROL_5_LIMIT;
+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
+}
+
+/* All CPUs including BSP will run the following function. */
+void soc_core_init(struct device *cpu)
+{
+ /* Clear out pending MCEs */
+ /* TODO(adurbin): This should only be done on a cold boot. Also, some
+ * of these banks are core vs package scope. For now every CPU clears
+ * every bank. */
+ mca_configure();
+
+ /* Enable the local CPU apics */
+ enable_lapic_tpr();
+ setup_lapic();
+
+ /* Configure c-state interrupt response time */
+ configure_c_states();
+
+ /* Configure Enhanced SpeedStep and Thermal Sensors */
+ configure_misc();
+
+ /* Configure Intel Speed Shift */
+ configure_isst();
+
+ /* Enable PM timer emulation */
+ enable_pm_timer_emulation();
+
+ /* Enable Direct Cache Access */
+ configure_dca_cap();
+
+ /* Set energy policy */
+ set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+ /* Enable Turbo */
+ enable_turbo();
+}
+
+static void per_cpu_smm_trigger(void)
+{
+ /* Relocate the SMM handler. */
+ smm_relocate();
+}
+
+static void post_mp_init(void)
+{
+ /* Set Max Ratio */
+ cpu_set_max_ratio();
+
+ /*
+ * Now that all APs have been relocated as well as the BSP let SMIs
+ * start flowing.
+ */
+ smm_southbridge_enable(PWRBTN_EN | GBL_EN);
+
+ /* Lock down the SMRAM space. */
+ smm_lock();
+}
+
+static const struct mp_ops mp_ops = {
+ /*
+ * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
+ * that are set prior to ramstage.
+ * Real MTRRs programming are being done after resource allocation.
+ */
+ .pre_mp_init = soc_fsp_load,
+ .get_cpu_count = get_cpu_count,
+ .get_smm_info = smm_info,
+ .get_microcode_info = get_microcode_info,
+ .pre_mp_smm_init = smm_initialize,
+ .per_cpu_smm_trigger = per_cpu_smm_trigger,
+ .relocation_handler = smm_relocation_handler,
+ .post_mp_init = post_mp_init,
+};
+
+void soc_init_cpus(struct bus *cpu_bus)
+{
+ if (mp_init_with_smm(cpu_bus, &mp_ops))
+ printk(BIOS_ERR, "MP initialization failure.\n");
+}
diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c
new file mode 100644
index 0000000000..903259497d
--- /dev/null
+++ b/src/soc/intel/jasperlake/elog.c
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootstate.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <stdint.h>
+#include <elog.h>
+#include <intelblocks/pmclib.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+
+static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
+{
+ int i;
+
+ gpe0_sts &= gpe0_en;
+
+ for (i = 0; i <= 31; i++) {
+ if (gpe0_sts & (1 << i))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
+ }
+}
+
+static void pch_log_wake_source(struct chipset_power_state *ps)
+{
+ /* Power Button */
+ if (ps->pm1_sts & PWRBTN_STS)
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
+
+ /* RTC */
+ if (ps->pm1_sts & RTC_STS)
+ elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
+
+ /* PCI Express (TODO: determine wake device) */
+ if (ps->pm1_sts & PCIEXPWAK_STS)
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
+
+ /* PME (TODO: determine wake device) */
+ if (ps->gpe0_sts[GPE_STD] & PME_STS)
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
+
+ /* Internal PME (TODO: determine wake device) */
+ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
+
+ /* SMBUS Wake */
+ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
+ elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
+
+ /* Log GPIO events in set 1-3 */
+ pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);
+ pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);
+ pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64);
+ /* Treat the STD as an extension of GPIO to obtain visibility. */
+ pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96);
+}
+
+static void pch_log_power_and_resets(struct chipset_power_state *ps)
+{
+ /* Thermal Trip */
+ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
+ elog_add_event(ELOG_TYPE_THERM_TRIP);
+
+ /* PWR_FLR Power Failure */
+ if (ps->gen_pmcon_a & PWR_FLR)
+ elog_add_event(ELOG_TYPE_POWER_FAIL);
+
+ /* SUS Well Power Failure */
+ if (ps->gen_pmcon_a & SUS_PWR_FLR)
+ elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
+
+ /* TCO Timeout */
+ if (ps->prev_sleep_state != ACPI_S3 &&
+ ps->tco2_sts & TCO_STS_SECOND_TO)
+ elog_add_event(ELOG_TYPE_TCO_RESET);
+
+ /* Power Button Override */
+ if (ps->pm1_sts & PRBTNOR_STS)
+ elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
+
+ /* RTC reset */
+ if (ps->gen_pmcon_b & RTC_BATTERY_DEAD)
+ elog_add_event(ELOG_TYPE_RTC_RESET);
+
+ /* Host Reset Status */
+ if (ps->gen_pmcon_a & HOST_RST_STS)
+ elog_add_event(ELOG_TYPE_SYSTEM_RESET);
+
+ /* ACPI Wake Event */
+ if (ps->prev_sleep_state != ACPI_S0)
+ elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
+}
+
+static void pch_log_state(void *unused)
+{
+ struct chipset_power_state *ps = pmc_get_power_state();
+
+ if (!ps) {
+ printk(BIOS_ERR, "chipset_power_state not found!\n");
+ return;
+ }
+
+ /* Power and Reset */
+ pch_log_power_and_resets(ps);
+
+ /* Wake Sources */
+ if (ps->prev_sleep_state > ACPI_S0)
+ pch_log_wake_source(ps);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL);
+
+void elog_gsmi_cb_platform_log_wake_source(void)
+{
+ struct chipset_power_state ps;
+ pmc_fill_pm_reg_info(&ps);
+ pch_log_wake_source(&ps);
+}
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c
new file mode 100644
index 0000000000..da36ea6304
--- /dev/null
+++ b/src/soc/intel/jasperlake/espi.c
@@ -0,0 +1,247 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 2
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <pc80/isa-dma.h>
+#include <pc80/i8259.h>
+#include <arch/io.h>
+#include <device/pci_ops.h>
+#include <arch/ioapic.h>
+#include <intelblocks/itss.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <reg_script.h>
+#include <soc/espi.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/soc_chip.h>
+
+/*
+* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
+* certain memory range as reserved range for BIOS usage.
+* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
+*/
+static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = {
+ { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
+ { 0, 0 }
+};
+
+const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
+{
+ return tgl_lpc_fixed_mmio_ranges;
+}
+
+void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
+{
+ const config_t *config = config_of(dev);
+
+ gen_io_dec[0] = config->gen1_dec;
+ gen_io_dec[1] = config->gen2_dec;
+ gen_io_dec[2] = config->gen3_dec;
+ gen_io_dec[3] = config->gen4_dec;
+}
+
+void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
+{
+ /* Mirror these same settings in DMI PCR */
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
+}
+
+uint8_t get_pch_series(void)
+{
+ uint16_t lpc_did_hi_byte;
+
+ /*
+ * Fetch upper 8 bits on ESPI device ID to determine PCH type
+ * Adding 1 to the offset to fetch upper 8 bits
+ */
+ lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1);
+
+ if (lpc_did_hi_byte == 0xA0)
+ return PCH_TGP;
+ else if (lpc_did_hi_byte == 0x4d)
+ return PCH_JSP;
+ else
+ return PCH_UNKNOWN_SERIES;
+}
+
+#if ENV_RAMSTAGE
+static void soc_mirror_dmi_pcr_io_dec(void)
+{
+ struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0);
+ uint32_t io_dec_arr[] = {
+ pci_read_config32(dev, ESPI_GEN1_DEC),
+ pci_read_config32(dev, ESPI_GEN2_DEC),
+ pci_read_config32(dev, ESPI_GEN3_DEC),
+ pci_read_config32(dev, ESPI_GEN4_DEC),
+ };
+ /* Mirror these same settings in DMI PCR */
+ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
+}
+
+static void pch_enable_ioapic(const struct device *dev)
+{
+ u32 reg32;
+ /* PCH-LP has 120 redirection entries */
+ const int redir_entries = 120;
+
+ set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
+
+ /* affirm full set of redirection table entries ("write once") */
+ reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
+
+ reg32 &= ~0x00ff0000;
+ reg32 |= (redir_entries - 1) << 16;
+
+ io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
+
+ /*
+ * Select Boot Configuration register (0x03) and
+ * use Processor System Bus (0x01) to deliver interrupts.
+ */
+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
+}
+/*
+ * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ * PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ * 0x80 - The PIRQ is not routed.
+ */
+
+void soc_pch_pirq_init(const struct device *dev)
+{
+ struct device *irq_dev;
+ uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
+
+ pch_interrupt_routing[0] = PCH_IRQ11;
+ pch_interrupt_routing[1] = PCH_IRQ10;
+ pch_interrupt_routing[2] = PCH_IRQ11;
+ pch_interrupt_routing[3] = PCH_IRQ11;
+ pch_interrupt_routing[4] = PCH_IRQ11;
+ pch_interrupt_routing[5] = PCH_IRQ11;
+ pch_interrupt_routing[6] = PCH_IRQ11;
+ pch_interrupt_routing[7] = PCH_IRQ11;
+
+ itss_irq_init(pch_interrupt_routing);
+
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ u8 int_pin = 0, int_line = 0;
+
+ if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+ continue;
+
+ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+
+ switch (int_pin) {
+ case 1: /* INTA# */
+ int_line = PCH_IRQ11;
+ break;
+ case 2: /* INTB# */
+ int_line = PCH_IRQ10;
+ break;
+ case 3: /* INTC# */
+ int_line = PCH_IRQ11;
+ break;
+ case 4: /* INTD# */
+ int_line = PCH_IRQ11;
+ break;
+ }
+
+ if (!int_line)
+ continue;
+
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+ }
+}
+
+static void pch_misc_init(void)
+{
+ uint8_t reg8;
+
+ /* Setup NMI on errors, disable SERR */
+ reg8 = (inb(0x61)) & 0xf0;
+ outb((reg8 | (1 << 2)), 0x61);
+
+ /* Disable NMI sources */
+ outb((1 << 7), 0x70);
+};
+
+void lpc_soc_init(struct device *dev)
+{
+ /* Legacy initialization */
+ isa_dma_init();
+ pch_misc_init();
+
+ /* Enable CLKRUN_EN for power gating ESPI */
+ lpc_enable_pci_clk_cntl();
+
+ /* Set ESPI Serial IRQ mode */
+ if (CONFIG(SERIRQ_CONTINUOUS_MODE))
+ lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
+ else
+ lpc_set_serirq_mode(SERIRQ_QUIET);
+
+ /* Interrupt configuration */
+ pch_enable_ioapic(dev);
+ soc_pch_pirq_init(dev);
+ setup_i8259();
+ i8259_configure_irq_trigger(9, 1);
+ soc_mirror_dmi_pcr_io_dec();
+}
+
+/* Fill up ESPI IO resource structure inside SoC directory */
+void pch_lpc_soc_fill_io_resources(struct device *dev)
+{
+ /*
+ * PMC pci device gets hidden from PCI bus due to Silicon
+ * policy hence bind ACPI BASE aka ABASE (offset 0x20) with
+ * ESPI IO resources to ensure that ABASE falls under PCI reserved
+ * IO memory range.
+ *
+ * Note: Don't add any more resource with same offset 0x20
+ * under this device space.
+ */
+ pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4,
+ ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
+}
+
+#endif
diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c
new file mode 100644
index 0000000000..b636ccbec0
--- /dev/null
+++ b/src/soc/intel/jasperlake/finalize.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 4, 29
+ */
+
+#include <arch/io.h>
+#include <device/mmio.h>
+#include <bootstate.h>
+#include <console/console.h>
+#include <console/post_codes.h>
+#include <cpu/x86/smm.h>
+#include <device/pci.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/tco.h>
+#include <intelblocks/thermal.h>
+#include <reg_script.h>
+#include <spi-generic.h>
+#include <soc/p2sb.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+#include <soc/smbus.h>
+#include <soc/soc_chip.h>
+#include <soc/systemagent.h>
+
+#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
+#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
+#define CAM_CLK_EN (1 << 1)
+#define MIPI_CLK (1 << 0)
+#define HDPLL_CLK (0 << 0)
+
+static void pch_enable_isclk(void)
+{
+ pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
+ pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
+}
+
+static void pch_handle_sideband(config_t *config)
+{
+ if (config->pch_isclk)
+ pch_enable_isclk();
+}
+
+static void pch_finalize(void)
+{
+ uint32_t reg32;
+ uint8_t *pmcbase;
+ config_t *config;
+ uint8_t reg8;
+
+ /* TCO Lock down */
+ tco_lockdown();
+
+ /* TODO: Add Thermal Configuration */
+
+ /*
+ * Disable ACPI PM timer based on dt policy
+ *
+ * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
+ * Disabling ACPI PM timer also switches off TCO
+ *
+ * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
+ * just required to get to chip config. PCH_DEV_PMC is hidden by this
+ * point and hence removed from the root bus. pcidev_path_on_root thus
+ * returns NULL for PCH_DEV_PMC device.
+ */
+ config = config_of_soc();
+ pmcbase = pmc_mmio_regs();
+ if (config->PmTimerDisabled) {
+ reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
+ reg8 |= (1 << 1);
+ write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
+ }
+
+ /* Disable XTAL shutdown qualification for low power idle. */
+ if (config->s0ix_enable) {
+ reg32 = read32(pmcbase + CPPMVRIC);
+ reg32 |= XTALSDQDIS;
+ write32(pmcbase + CPPMVRIC, reg32);
+ }
+
+ pch_handle_sideband(config);
+
+ pmc_clear_pmcon_sts();
+}
+
+static void soc_finalize(void *unused)
+{
+ printk(BIOS_DEBUG, "Finalizing chipset.\n");
+
+ pch_finalize();
+
+ printk(BIOS_DEBUG, "Finalizing SMM.\n");
+ outb(APM_CNT_FINALIZE, APM_CNT);
+
+ /* Indicate finalize step with post code */
+ post_code(POST_OS_BOOT);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
diff --git a/src/soc/intel/jasperlake/fsp_params_jsl.c b/src/soc/intel/jasperlake/fsp_params_jsl.c
new file mode 100644
index 0000000000..932bd06ff7
--- /dev/null
+++ b/src/soc/intel/jasperlake/fsp_params_jsl.c
@@ -0,0 +1,191 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <assert.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <fsp/ppi/mp_service_ppi.h>
+#include <fsp/util.h>
+#include <intelblocks/lpss.h>
+#include <intelblocks/mp_init.h>
+#include <intelblocks/xdci.h>
+#include <soc/intel/common/vbt.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
+
+static const pci_devfn_t serial_io_dev[] = {
+ PCH_DEVFN_I2C0,
+ PCH_DEVFN_I2C1,
+ PCH_DEVFN_I2C2,
+ PCH_DEVFN_I2C3,
+ PCH_DEVFN_I2C4,
+ PCH_DEVFN_I2C5,
+ PCH_DEVFN_GSPI0,
+ PCH_DEVFN_GSPI1,
+ PCH_DEVFN_GSPI2,
+ PCH_DEVFN_UART0,
+ PCH_DEVFN_UART1,
+ PCH_DEVFN_UART2
+};
+
+static void parse_devicetree(FSP_S_CONFIG *params)
+{
+ const struct soc_intel_tigerlake_config *config = config_of_soc();
+
+ /* LPSS controllers configuration */
+
+ /* I2C */
+ _Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >=
+ ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!");
+ memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode,
+ sizeof(config->SerialIoI2cMode));
+
+ /* GSPI */
+ _Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >=
+ ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!");
+ memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode,
+ sizeof(config->SerialIoGSpiMode));
+
+ _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >=
+ ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!");
+ memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode,
+ sizeof(config->SerialIoGSpiCsMode));
+
+ _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >=
+ ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!");
+ memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState,
+ sizeof(config->SerialIoGSpiCsState));
+
+ /* UART */
+ _Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >=
+ ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!");
+ memcpy(params->SerialIoUartMode, config->SerialIoUartMode,
+ sizeof(config->SerialIoUartMode));
+}
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
+{
+ unsigned int i;
+ struct device *dev;
+ FSP_S_CONFIG *params = &supd->FspsConfig;
+ struct soc_intel_tigerlake_config *config = config_of_soc();
+
+ /* Parse device tree and fill in FSP UPDs */
+ parse_devicetree(params);
+
+ /* Load VBT before devicetree-specific config. */
+ params->GraphicsConfigPtr = (uintptr_t)vbt_get();
+
+ /* Check if IGD is present and fill Graphics init param accordingly */
+ dev = pcidev_path_on_root(SA_DEVFN_IGD);
+
+ if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
+ params->PeiGraphicsPeimInit = 1;
+ else
+ params->PeiGraphicsPeimInit = 0;
+
+ /* Use coreboot MP PPI services if Kconfig is enabled */
+ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
+ params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+ params->SkipMpInit = 0;
+ } else {
+ params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
+ }
+
+ /* Unlock upper 8 bytes of RTC RAM */
+ params->RtcMemoryLock = 0;
+
+ /* Legacy 8254 timer support */
+ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
+ params->Enable8254ClockGatingOnS3 = 1;
+
+ /* disable Legacy PME */
+ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+
+ /* USB configuration */
+ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
+
+ params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
+ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+ params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
+ params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
+ params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
+ params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
+
+ params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ if (config->usb3_ports[i].tx_de_emp) {
+ params->Usb3HsioTxDeEmphEnable[i] = 1;
+ params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
+ }
+ if (config->usb3_ports[i].tx_downscale_amp) {
+ params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
+ params->Usb3HsioTxDownscaleAmp[i] =
+ config->usb3_ports[i].tx_downscale_amp;
+ }
+ }
+
+ /* SDCard related configuration */
+ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
+ if (!dev)
+ params->ScsSdCardEnabled = 0;
+ else
+ params->ScsSdCardEnabled = dev->enabled;
+
+ params->Device4Enable = config->Device4Enable;
+
+ /* eMMC configuration */
+ dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
+ if (!dev) {
+ params->ScsEmmcEnabled = 0;
+ } else {
+ params->ScsEmmcEnabled = dev->enabled;
+ params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+ }
+
+ /* Enable xDCI controller if enabled in devicetree and allowed */
+ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
+ if (dev) {
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+
+ params->XdciEnable = dev->enabled;
+ } else {
+ params->XdciEnable = 0;
+ }
+
+ /* Provide correct UART number for FSP debug logs */
+ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
+
+ /* Override/Fill FSP Silicon Param for mainboard */
+ mainboard_silicon_init_params(params);
+}
+
+/* Mainboard GPIO Configuration */
+__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Return list of SOC LPSS controllers */
+const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
+{
+ *size = ARRAY_SIZE(serial_io_dev);
+ return serial_io_dev;
+}
diff --git a/src/soc/intel/jasperlake/fsp_params_tgl.c b/src/soc/intel/jasperlake/fsp_params_tgl.c
new file mode 100644
index 0000000000..a8be407d23
--- /dev/null
+++ b/src/soc/intel/jasperlake/fsp_params_tgl.c
@@ -0,0 +1,212 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <intelblocks/lpss.h>
+#include <intelblocks/xdci.h>
+#include <soc/gpio_soc_defs.h>
+#include <soc/intel/common/vbt.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
+
+/*
+ * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
+ * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
+ * In order to ensure that mainboard setting does not disable L1 substates
+ * incorrectly, chip config parameter values are offset by 1 with 0 meaning
+ * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
+ * value is set in fsp_params.
+ * 0: Use FSP UPD default
+ * 1: Disable L1 substates
+ * 2: Use L1.1
+ * 3: Use L1.2 (FSP UPD default)
+ */
+static int get_l1_substate_control(enum L1_substates_control ctl)
+{
+ if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
+ ctl = L1_SS_L1_2;
+ return ctl - 1;
+}
+
+static void parse_devicetree(FSP_S_CONFIG *params)
+{
+ const struct soc_intel_tigerlake_config *config;
+ config = config_of_soc();
+
+ for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
+ params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
+
+ for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
+ params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
+ params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
+ params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
+ }
+
+ for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
+ params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
+}
+
+static const pci_devfn_t serial_io_dev[] = {
+ PCH_DEVFN_I2C0,
+ PCH_DEVFN_I2C1,
+ PCH_DEVFN_I2C2,
+ PCH_DEVFN_I2C3,
+ PCH_DEVFN_I2C4,
+ PCH_DEVFN_I2C5,
+ PCH_DEVFN_GSPI0,
+ PCH_DEVFN_GSPI1,
+ PCH_DEVFN_GSPI2,
+ PCH_DEVFN_GSPI3,
+ PCH_DEVFN_UART0,
+ PCH_DEVFN_UART1,
+ PCH_DEVFN_UART2
+};
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
+{
+ int i;
+ FSP_S_CONFIG *params = &supd->FspsConfig;
+
+ struct device *dev;
+ struct soc_intel_tigerlake_config *config;
+ config = config_of_soc();
+
+ /* Parse device tree and enable/disable Serial I/O devices */
+ parse_devicetree(params);
+
+ /* Load VBT before devicetree-specific config. */
+ params->GraphicsConfigPtr = (uintptr_t)vbt_get();
+
+ params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
+
+ dev = pcidev_path_on_root(SA_DEVFN_IGD);
+ if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
+ params->PeiGraphicsPeimInit = 1;
+ else
+ params->PeiGraphicsPeimInit = 0;
+
+ for (i = 0; i < 8; i++)
+ params->IomTypeCPortPadCfg[i] = 0x09000000;
+
+ /* USB */
+ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
+ params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
+ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+ params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
+ params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
+ params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
+ params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
+ params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ if (config->usb3_ports[i].tx_de_emp) {
+ params->Usb3HsioTxDeEmphEnable[i] = 1;
+ params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
+ }
+ if (config->usb3_ports[i].tx_downscale_amp) {
+ params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
+ params->Usb3HsioTxDownscaleAmp[i] =
+ config->usb3_ports[i].tx_downscale_amp;
+ }
+ }
+
+ /* RP Configs */
+ for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)
+ params->PcieRpL1Substates[i] =
+ get_l1_substate_control(config->PcieRpL1Substates[i]);
+
+ /* Enable xDCI controller if enabled in devicetree and allowed */
+ dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
+ if (dev) {
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+ params->XdciEnable = dev->enabled;
+ } else {
+ params->XdciEnable = 0;
+ }
+
+ /* PCH UART selection for FSP Debug */
+ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
+ ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
+ params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
+
+ /* SATA */
+ dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
+ if (!dev)
+ params->SataEnable = 0;
+ else {
+ params->SataEnable = dev->enabled;
+ params->SataMode = config->SataMode;
+ params->SataSalpSupport = config->SataSalpSupport;
+ memcpy(params->SataPortsEnable, config->SataPortsEnable,
+ sizeof(params->SataPortsEnable));
+ memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
+ sizeof(params->SataPortsDevSlp));
+ }
+
+ /* LAN */
+ dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
+ if (!dev)
+ params->PchLanEnable = 0;
+ else
+ params->PchLanEnable = dev->enabled;
+
+ /* CNVi */
+ dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI);
+ if (dev)
+ params->CnviMode = dev->enabled;
+ else
+ params->CnviMode = 0;
+
+ /* Legacy 8254 timer support */
+ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
+ params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
+
+ /* Enable Hybrid storage auto detection */
+ params->HybridStorageMode = config->HybridStorageMode;
+
+ /* USB4/TBT */
+ for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {
+ dev = pcidev_on_root(SA_DEV_SLOT_TBT, i);
+ if (dev)
+ params->ITbtPcieRootPortEn[i] = dev->enabled;
+ else
+ params->ITbtPcieRootPortEn[i] = 0;
+ }
+
+ mainboard_silicon_init_params(params);
+}
+
+/* Mainboard GPIO Configuration */
+__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Return list of SOC LPSS controllers */
+const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
+{
+ *size = ARRAY_SIZE(serial_io_dev);
+ return serial_io_dev;
+}
diff --git a/src/soc/intel/jasperlake/gpio_jsl.c b/src/soc/intel/jasperlake/gpio_jsl.c
new file mode 100644
index 0000000000..afb9f7b3bc
--- /dev/null
+++ b/src/soc/intel/jasperlake/gpio_jsl.c
@@ -0,0 +1,210 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pmc.h>
+
+static const struct reset_mapping rst_map[] = {
+ { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+
+static const struct reset_mapping rst_map_com0[] = {
+ { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
+};
+
+/*
+ * The GPIO driver for Jasperlake on Windows/Linux expects 32 GPIOs per pad
+ * group, regardless of whether or not there is a physical pad for each
+ * exposed GPIO number.
+ *
+ * This results in the OS having a sparse GPIO map, and devices that need
+ * to export an ACPI GPIO must use the OS expected number.
+ *
+ * Not all pins are usable as GPIO and those groups do not have a pad base.
+ *
+ * This layout matches the Linux kernel pinctrl map for JSP at:
+ * linux/drivers/pinctrl/intel/pinctrl-jasperlake.c
+ */
+static const struct pad_group jsl_community0_groups[] = {
+
+ INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 0), /* GPP_F */
+ INTEL_GPP(GPP_F0, GPIO_RSVD_0, GPIO_RSVD_8),
+ INTEL_GPP_BASE(GPP_F0, GPP_B0, GPP_B23, 32), /* GPP_B */
+ INTEL_GPP(GPP_F0, GPIO_RSVD_9, GPIO_RSVD_10),
+ INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_RSVD_11, 64), /* GPP_A */
+ INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */
+ INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */
+};
+
+static const struct pad_group jsl_community1_groups[] = {
+ INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 160), /* GPP_H */
+ INTEL_GPP_BASE(GPP_H0, GPP_D0, GPP_D23, 192), /* GPP_D */
+ INTEL_GPP(GPP_H0, GPIO_RSVD_12, GPIO_RSVD_13),
+ INTEL_GPP_BASE(GPP_H0, VGPIO_0, VGPIO_39, 224), /* VGPIO */
+ INTEL_GPP_BASE(GPP_H0, GPP_C0, GPP_C23, 256), /* GPP_C */
+};
+
+/* This community is not visible to the OS */
+static const struct pad_group jsl_community2_groups[] = {
+ INTEL_GPP(GPD0, GPD0, GPD10), /* GPD */
+ INTEL_GPP(GPD0, GPIO_RSVD_14, GPIO_RSVD_17),
+};
+
+
+static const struct pad_group jsl_community4_groups[] = {
+ INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_18, GPIO_RSVD_23),
+ INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288), /* GPP_E */
+ INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_24, GPIO_RSVD_36),
+};
+
+
+static const struct pad_group jsl_community5_groups[] = {
+ INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 320), /* GPP_G */
+};
+
+static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = {
+ /* GPP F, B, A, S, R */
+ [COMM_0] = {
+ .port = PID_GPIOCOM0,
+ .first_pad = GPP_F0,
+ .last_pad = GPP_R7,
+ .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_FBASR",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map_com0,
+ .num_reset_vals = ARRAY_SIZE(rst_map_com0),
+ .groups = jsl_community0_groups,
+ .num_groups = ARRAY_SIZE(jsl_community0_groups),
+ },
+ /* GPP H, D, VGPIO, C */
+ [COMM_1] = {
+ .port = PID_GPIOCOM1,
+ .first_pad = GPP_H0,
+ .last_pad = GPP_C23,
+ .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_HDC",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = jsl_community1_groups,
+ .num_groups = ARRAY_SIZE(jsl_community1_groups),
+ },
+ /* GPD */
+ [COMM_2] = {
+ .port = PID_GPIOCOM2,
+ .first_pad = GPD0,
+ .last_pad = GPIO_RSVD_17,
+ .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPD",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = jsl_community2_groups,
+ .num_groups = ARRAY_SIZE(jsl_community2_groups),
+ },
+ /* GPP E */
+ [COMM_4] = {
+ .port = PID_GPIOCOM4,
+ .first_pad = GPIO_RSVD_18,
+ .last_pad = GPIO_RSVD_36,
+ .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_E",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = jsl_community4_groups,
+ .num_groups = ARRAY_SIZE(jsl_community4_groups),
+ },
+ /* GPP G */
+ [COMM_5] = {
+ .port = PID_GPIOCOM5,
+ .first_pad = GPP_G0,
+ .last_pad = GPP_G7,
+ .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_G",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = jsl_community5_groups,
+ .num_groups = ARRAY_SIZE(jsl_community5_groups),
+ }
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+ *num_communities = ARRAY_SIZE(jsl_communities);
+ return jsl_communities;
+}
+
+const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
+{
+ static const struct pmc_to_gpio_route routes[] = {
+ { PMC_GPP_A, GPP_A },
+ { PMC_GPP_B, GPP_B },
+ { PMC_GPP_R, GPP_R },
+ { PMC_GPP_D, GPP_D },
+ { PMC_GPP_S, GPP_S },
+ { PMC_GPP_H, GPP_H },
+ { PMC_GPD, GPP_GPD },
+ { PMC_GPP_C, GPP_C },
+ { PMC_GPP_E, GPP_E },
+ { PMC_GPP_F, GPP_F }
+ };
+
+ *num = ARRAY_SIZE(routes);
+ return routes;
+}
diff --git a/src/soc/intel/jasperlake/gpio_tgl.c b/src/soc/intel/jasperlake/gpio_tgl.c
new file mode 100644
index 0000000000..cfdd0ac465
--- /dev/null
+++ b/src/soc/intel/jasperlake/gpio_tgl.c
@@ -0,0 +1,197 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pmc.h>
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 27
+ */
+
+static const struct reset_mapping rst_map[] = {
+ { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+static const struct reset_mapping rst_map_com2[] = {
+ { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
+};
+
+/*
+ * This layout matches the Linux kernel pinctrl map for TGL-LP at:
+ * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
+ */
+static const struct pad_group tgl_community0_groups[] = {
+ INTEL_GPP(GPP_B0, GPP_B0, GPP_B25), /* GPP_B */
+ INTEL_GPP(GPP_B0, GPP_T0, GPP_T15), /* GPP_T */
+ INTEL_GPP(GPP_B0, GPP_A0, GPP_A24), /* GPP_A */
+};
+
+static const struct pad_group tgl_community1_groups[] = {
+ INTEL_GPP(GPP_S0, GPP_S0, GPP_S7), /* GPP_S */
+ INTEL_GPP(GPP_S0, GPP_H0, GPP_H23), /* GPP_H */
+ INTEL_GPP(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK), /* GPP_D */
+ INTEL_GPP(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK), /* GPP_U */
+ INTEL_GPP(GPP_S0, CNV_BTEN, vI2S2_RXD), /* GPP_VGPIO */
+};
+
+/* This community is not visible to the OS */
+static const struct pad_group tgl_community2_groups[] = {
+ INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */
+};
+
+static const struct pad_group tgl_community4_groups[] = {
+ INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */
+ INTEL_GPP(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK), /* GPP_F */
+ INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */
+ INTEL_GPP(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK), /* GPP_E */
+ INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE), /* GPP_JTAG */
+};
+
+static const struct pad_group tgl_community5_groups[] = {
+ INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */
+ INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */
+};
+
+static const struct pad_community tgl_communities[] = {
+ [COMM_0] = { /* GPP B, T, A */
+ .port = PID_GPIOCOM0,
+ .first_pad = GPP_B0,
+ .last_pad = GPP_A24,
+ .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_BTA",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = tgl_community0_groups,
+ .num_groups = ARRAY_SIZE(tgl_community0_groups),
+ },
+ [COMM_1] = { /* GPP S, D, H, U, VGPIO */
+ .port = PID_GPIOCOM1,
+ .first_pad = GPP_S0,
+ .last_pad = vI2S2_RXD,
+ .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_SDHU",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = tgl_community1_groups,
+ .num_groups = ARRAY_SIZE(tgl_community1_groups),
+ },
+ [COMM_2] = { /* GPD */
+ .port = PID_GPIOCOM2,
+ .first_pad = GPD0,
+ .last_pad = GPD_DRAM_RESETB,
+ .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPD",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map_com2,
+ .num_reset_vals = ARRAY_SIZE(rst_map_com2),
+ .groups = tgl_community2_groups,
+ .num_groups = ARRAY_SIZE(tgl_community2_groups),
+ },
+ [COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */
+ .port = PID_GPIOCOM4,
+ .first_pad = GPP_C0,
+ .last_pad = GPP_DBG_PMODE,
+ .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_FCE",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = tgl_community4_groups,
+ .num_groups = ARRAY_SIZE(tgl_community4_groups),
+ },
+ [COMM_5] = { /* GPP R, SPI */
+ .port = PID_GPIOCOM5,
+ .first_pad = GPP_R0,
+ .last_pad = GPP_CLK_LOOPBK,
+ .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_CPU_VBPIO",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = tgl_community5_groups,
+ .num_groups = ARRAY_SIZE(tgl_community5_groups),
+ }
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+ *num_communities = ARRAY_SIZE(tgl_communities);
+ return tgl_communities;
+}
+
+const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
+{
+ static const struct pmc_to_gpio_route routes[] = {
+ { PMC_GPP_B, GPP_B },
+ { PMC_GPP_T, GPP_T },
+ { PMC_GPP_A, GPP_A },
+ { PMC_GPP_R, GPP_R },
+ { PMC_GPD, GPD },
+ { PMC_GPP_S, GPP_S },
+ { PMC_GPP_H, GPP_H },
+ { PMC_GPP_D, GPP_D },
+ { PMC_GPP_U, GPP_U },
+ { PMC_GPP_F, GPP_F },
+ { PMC_GPP_C, GPP_C },
+ { PMC_GPP_E, GPP_E },
+ };
+ *num = ARRAY_SIZE(routes);
+ return routes;
+}
diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c
new file mode 100644
index 0000000000..fef17e17e8
--- /dev/null
+++ b/src/soc/intel/jasperlake/graphics.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor SA Datasheet
+ * Document number: 571131
+ * Chapter number: 4
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <drivers/intel/gma/i915_reg.h>
+#include <drivers/intel/gma/opregion.h>
+#include <intelblocks/graphics.h>
+#include <types.h>
+
+uintptr_t fsp_soc_get_igd_bar(void)
+{
+ return graphics_get_memory_base();
+}
+
+void graphics_soc_init(struct device *dev)
+{
+ uint32_t ddi_buf_ctl;
+
+ /* Skip IGD GT programming */
+ if (CONFIG(SKIP_GRAPHICS_ENABLING))
+ return;
+
+ /*
+ * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
+ * This will allow the kernel to use 4-lane eDP links properly
+ * if the VBIOS or GOP driver do not execute.
+ */
+ ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
+ if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
+ ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED |
+ DDI_BUF_IS_IDLE);
+ graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
+ }
+
+ /*
+ * GFX PEIM module inside FSP binary is taking care of graphics
+ * initialization based on RUN_FSP_GOP Kconfig
+ * option and input VBT file. Hence no need to load/execute legacy VGA
+ * OpROM in order to initialize GFX.
+ *
+ * In case of non-FSP solution, SoC need to select VGA_ROM_RUN
+ * Kconfig to perform GFX initialization through VGA OpRom.
+ */
+ if (CONFIG(RUN_FSP_GOP))
+ return;
+
+ /* IGD needs to Bus Master */
+ uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* Initialize PCI device, load/execute BIOS Option ROM */
+ pci_dev_init(dev);
+}
+
+uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
+ uintptr_t current, struct acpi_rsdp *rsdp)
+{
+ igd_opregion_t *opregion;
+
+ printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
+ opregion = (igd_opregion_t *)current;
+
+ if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
+ return current;
+
+ current += sizeof(igd_opregion_t);
+
+ return acpi_align_current(current);
+}
diff --git a/src/soc/intel/jasperlake/gspi.c b/src/soc/intel/jasperlake/gspi.c
new file mode 100644
index 0000000000..1381fb2499
--- /dev/null
+++ b/src/soc/intel/jasperlake/gspi.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 11
+ */
+
+#include <intelblocks/gspi.h>
+#include <soc/pci_devs.h>
+
+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
+{
+ switch (gspi_bus) {
+ case 0:
+ return PCH_DEVFN_GSPI0;
+ case 1:
+ return PCH_DEVFN_GSPI1;
+ case 2:
+ return PCH_DEVFN_GSPI2;
+ }
+ return -1;
+}
diff --git a/src/soc/intel/jasperlake/i2c.c b/src/soc/intel/jasperlake/i2c.c
new file mode 100644
index 0000000000..46bc726726
--- /dev/null
+++ b/src/soc/intel/jasperlake/i2c.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 13
+ */
+
+#include <device/device.h>
+#include <drivers/i2c/designware/dw_i2c.h>
+#include <soc/pci_devs.h>
+
+int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
+{
+ switch (devfn) {
+ case PCH_DEVFN_I2C0:
+ return 0;
+ case PCH_DEVFN_I2C1:
+ return 1;
+ case PCH_DEVFN_I2C2:
+ return 2;
+ case PCH_DEVFN_I2C3:
+ return 3;
+ case PCH_DEVFN_I2C4:
+ return 4;
+ case PCH_DEVFN_I2C5:
+ return 5;
+ }
+ return -1;
+}
+
+int dw_i2c_soc_bus_to_devfn(unsigned int bus)
+{
+ switch (bus) {
+ case 0:
+ return PCH_DEVFN_I2C0;
+ case 1:
+ return PCH_DEVFN_I2C1;
+ case 2:
+ return PCH_DEVFN_I2C2;
+ case 3:
+ return PCH_DEVFN_I2C3;
+ case 4:
+ return PCH_DEVFN_I2C4;
+ case 5:
+ return PCH_DEVFN_I2C5;
+ }
+ return -1;
+}
diff --git a/src/soc/intel/jasperlake/include/soc/bootblock.h b/src/soc/intel/jasperlake/include/soc/bootblock.h
new file mode 100644
index 0000000000..0c8d8c201a
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/bootblock.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_TIGERLAKE_BOOTBLOCK_H_
+#define _SOC_TIGERLAKE_BOOTBLOCK_H_
+
+/* Bootblock pre console init programming */
+void bootblock_cpu_init(void);
+void bootblock_pch_early_init(void);
+
+/* Bootblock post console init programming */
+void pch_init(void);
+void pch_early_iorange_init(void);
+void report_platform_info(void);
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h
new file mode 100644
index 0000000000..799382498b
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/cpu.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_TIGERLAKE_CPU_H_
+#define _SOC_TIGERLAKE_CPU_H_
+
+#include <intelblocks/msr.h>
+
+/* Latency times in units of 32768ns */
+#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d
+#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d
+#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d
+#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d
+#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d
+#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d
+
+/* Power in units of mW */
+#define C1_POWER 0x3e8
+#define C6_POWER 0x15e
+#define C7_POWER 0xc8
+#define C8_POWER 0xc8
+#define C9_POWER 0xc8
+#define C10_POWER 0xc8
+
+/* Common Timer Copy (CTC) frequency - 38.4MHz. */
+#define CTC_FREQ 38400000
+
+#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
+ (((1 << ((base)*5)) * (limit)) / 1000)
+#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
+ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
+ (IRTL_1024_NS >> 10))
+
+/* Configure power limits for turbo mode */
+void set_power_limits(u8 power_limit_1_time);
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/espi.h b/src/soc/intel/jasperlake/include/soc/espi.h
new file mode 100644
index 0000000000..3f7e32a717
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/espi.h
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 2
+ */
+
+#ifndef _SOC_TIGERLAKE_ESPI_H_
+#define _SOC_TIGERLAKE_ESPI_H_
+
+#include <stdint.h>
+
+/* PCI Configuration Space (D31:F0): ESPI */
+#define SCI_IRQ_SEL (7 << 0)
+#define SCIS_IRQ9 0
+#define SCIS_IRQ10 1
+#define SCIS_IRQ11 2
+#define SCIS_IRQ20 4
+#define SCIS_IRQ21 5
+#define SCIS_IRQ22 6
+#define SCIS_IRQ23 7
+#define SERIRQ_CNTL 0x64
+#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/
+#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/
+#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */
+#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */
+#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */
+#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */
+#define LGMR 0x98 /* ESPI Generic Memory Range */
+#define PCCTL 0xE0 /* PCI Clock Control */
+#define CLKRUN_EN (1 << 0)
+
+/*
+ * This function will help to differentiate between 2 PCH on single type of soc.
+ * Since same soc may have LP series pch or H series PCH, we need to
+ * differentiate by reading upper 8 bits of PCH device ids.
+ *
+ * Return:
+ * Return PCH_LP or PCH_H macro in case of respective device ID found.
+ * PCH_UNKNOWN_SERIES in case of invalid device ID.
+ */
+uint8_t get_pch_series(void);
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpe.h b/src/soc/intel/jasperlake/include/soc/gpe.h
new file mode 100644
index 0000000000..c37750b1c4
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/gpe.h
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_GPE_H_
+#define _SOC_GPE_H_
+
+/* GPE_31_0 */
+#define GPE0_DW0_00 0
+#define GPE0_DW0_01 1
+#define GPE0_DW0_02 2
+#define GPE0_DW0_03 3
+#define GPE0_DW0_04 4
+#define GPE0_DW0_05 5
+#define GPE0_DW0_06 6
+#define GPE0_DW0_07 7
+#define GPE0_DW0_08 8
+#define GPE0_DW0_09 9
+#define GPE0_DW0_10 10
+#define GPE0_DW0_11 11
+#define GPE0_DW0_12 12
+#define GPE0_DW0_13 13
+#define GPE0_DW0_14 14
+#define GPE0_DW0_15 15
+#define GPE0_DW0_16 16
+#define GPE0_DW0_17 17
+#define GPE0_DW0_18 18
+#define GPE0_DW0_19 19
+#define GPE0_DW0_20 20
+#define GPE0_DW0_21 21
+#define GPE0_DW0_22 22
+#define GPE0_DW0_23 23
+#define GPE0_DW0_24 24
+#define GPE0_DW0_25 25
+#define GPE0_DW0_26 26
+#define GPE0_DW0_27 27
+#define GPE0_DW0_28 28
+#define GPE0_DW0_29 29
+#define GPE0_DW0_30 30
+#define GPE0_DW0_31 31
+/* GPE_63_32 */
+#define GPE0_DW1_00 32
+#define GPE0_DW1_01 33
+#define GPE0_DW1_02 34
+#define GPE0_DW1_03 36
+#define GPE0_DW1_04 36
+#define GPE0_DW1_05 37
+#define GPE0_DW1_06 38
+#define GPE0_DW1_07 39
+#define GPE0_DW1_08 40
+#define GPE0_DW1_09 41
+#define GPE0_DW1_10 42
+#define GPE0_DW1_11 43
+#define GPE0_DW1_12 44
+#define GPE0_DW1_13 45
+#define GPE0_DW1_14 46
+#define GPE0_DW1_15 47
+#define GPE0_DW1_16 48
+#define GPE0_DW1_17 49
+#define GPE0_DW1_18 50
+#define GPE0_DW1_19 51
+#define GPE0_DW1_20 52
+#define GPE0_DW1_21 53
+#define GPE0_DW1_22 54
+#define GPE0_DW1_23 55
+#define GPE0_DW1_24 56
+#define GPE0_DW1_25 57
+#define GPE0_DW1_26 58
+#define GPE0_DW1_27 59
+#define GPE0_DW1_28 60
+#define GPE0_DW1_29 61
+#define GPE0_DW1_30 62
+#define GPE0_DW1_31 63
+/* GPE_95_64 */
+#define GPE0_DW2_00 64
+#define GPE0_DW2_01 65
+#define GPE0_DW2_02 66
+#define GPE0_DW2_03 67
+#define GPE0_DW2_04 68
+#define GPE0_DW2_05 69
+#define GPE0_DW2_06 70
+#define GPE0_DW2_07 71
+#define GPE0_DW2_08 72
+#define GPE0_DW2_09 73
+#define GPE0_DW2_10 74
+#define GPE0_DW2_11 75
+#define GPE0_DW2_12 76
+#define GPE0_DW2_13 77
+#define GPE0_DW2_14 78
+#define GPE0_DW2_15 79
+#define GPE0_DW2_16 80
+#define GPE0_DW2_17 81
+#define GPE0_DW2_18 82
+#define GPE0_DW2_19 83
+#define GPE0_DW2_20 84
+#define GPE0_DW2_21 85
+#define GPE0_DW2_22 86
+#define GPE0_DW2_23 87
+#define GPE0_DW2_24 88
+#define GPE0_DW2_25 89
+#define GPE0_DW2_26 90
+#define GPE0_DW2_27 91
+#define GPE0_DW2_28 92
+#define GPE0_DW2_29 93
+#define GPE0_DW2_30 94
+#define GPE0_DW2_31 95
+/* GPE_STD */
+#define GPE0_HOT_PLUG 97
+#define GPE0_SWGPE 98
+#define GPE0_TCOSCI 102
+#define GPE0_SMB_WAK 103
+#define GPE0_PCI_EXP 105
+#define GPE0_BATLOW 106
+#define GPE0_PME 107
+#define GPE0_ME_SCI 108
+#define GPE0_PME_B0 109
+#define GPE0_ESPI 110
+#define GPE0_GPIO_T2 111
+#define GPE0_LAN_WAK 112
+#define GPE0_WADT 114
+
+#define GPE_MAX GPE0_WADT
+#endif /* _SOC_GPE_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/gpio.h b/src/soc/intel/jasperlake/include/soc/gpio.h
new file mode 100644
index 0000000000..fb3f42fd67
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/gpio.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_TIGERLAKE_GPIO_H_
+#define _SOC_TIGERLAKE_GPIO_H_
+
+#include <soc/gpio_defs.h>
+#include <intelblocks/gpio.h>
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
+
+ #define CROS_GPIO_NAME "INT34C5"
+ #define CROS_GPIO_COMM0_NAME "INT34C5:00"
+ #define CROS_GPIO_COMM1_NAME "INT34C5:01"
+ #define CROS_GPIO_COMM4_NAME "INT34C5:02"
+ #define CROS_GPIO_COMM5_NAME "INT34C5:03"
+
+#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY)
+
+ #define CROS_GPIO_NAME "INT34C8"
+ #define CROS_GPIO_COMM0_NAME "INT34C8:00"
+ #define CROS_GPIO_COMM1_NAME "INT34C8:01"
+ #define CROS_GPIO_COMM4_NAME "INT34C8:02"
+ #define CROS_GPIO_COMM5_NAME "INT34C8:03"
+#endif
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_defs.h
new file mode 100644
index 0000000000..2898c12ee0
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/gpio_defs.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_
+#define _SOC_TIGERLAKE_GPIO_DEFS_H_
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
+ #include <soc/gpio_defs_tgl.h>
+#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY)
+ #include <soc/gpio_defs_jsl.h>
+#endif
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h b/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h
new file mode 100644
index 0000000000..69ed539cae
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h
@@ -0,0 +1,272 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_JASPERLAKE_GPIO_DEFS_H_
+#define _SOC_JASPERLAKE_GPIO_DEFS_H_
+
+#ifndef __ACPI__
+#include <stddef.h>
+#endif
+#include <soc/gpio_soc_defs_jsl.h>
+
+
+#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
+
+#define NUM_GPIO_COMx_GPI_REGS(n) \
+ (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
+#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
+#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
+
+#define NUM_GPI_STATUS_REGS \
+ ((NUM_GPIO_COM0_GPI_REGS) +\
+ (NUM_GPIO_COM1_GPI_REGS) +\
+ (NUM_GPIO_COM2_GPI_REGS) +\
+ (NUM_GPIO_COM4_GPI_REGS) +\
+ (NUM_GPIO_COM5_GPI_REGS))
+/*
+ * IOxAPIC IRQs for the GPIOs
+ */
+
+/* Group F */
+#define GPP_F0_IRQ 0x40
+#define GPP_F1_IRQ 0x41
+#define GPP_F2_IRQ 0x42
+#define GPP_F3_IRQ 0x43
+#define GPP_F4_IRQ 0x44
+#define GPP_F5_IRQ 0x45
+#define GPP_F6_IRQ 0x46
+#define GPP_F7_IRQ 0x47
+#define GPP_F8_IRQ 0x48
+#define GPP_F9_IRQ 0x49
+#define GPP_F10_IRQ 0x4a
+#define GPP_F11_IRQ 0x4b
+#define GPP_F12_IRQ 0x4c
+#define GPP_F13_IRQ 0x4d
+#define GPP_F14_IRQ 0x4e
+#define GPP_F15_IRQ 0x4f
+#define GPP_F16_IRQ 0x50
+#define GPP_F17_IRQ 0x51
+#define GPP_F18_IRQ 0x52
+#define GPP_F19_IRQ 0x53
+
+/* Group G */
+#define GPP_G0_IRQ 0x18
+#define GPP_G1_IRQ 0x19
+#define GPP_G2_IRQ 0x1a
+#define GPP_G3_IRQ 0x1b
+#define GPP_G4_IRQ 0x1c
+#define GPP_G5_IRQ 0x1d
+#define GPP_G6_IRQ 0x1e
+#define GPP_G7_IRQ 0x1f
+
+/* Group B */
+#define GPP_B0_IRQ 0x20
+#define GPP_B1_IRQ 0x21
+#define GPP_B2_IRQ 0x22
+#define GPP_B3_IRQ 0x23
+#define GPP_B4_IRQ 0x24
+#define GPP_B5_IRQ 0x25
+#define GPP_B6_IRQ 0x26
+#define GPP_B7_IRQ 0x27
+#define GPP_B8_IRQ 0x28
+#define GPP_B9_IRQ 0x29
+#define GPP_B10_IRQ 0x2a
+#define GPP_B11_IRQ 0x2b
+#define GPP_B12_IRQ 0x2c
+#define GPP_B13_IRQ 0x2d
+#define GPP_B14_IRQ 0x2e
+#define GPP_B15_IRQ 0x2f
+#define GPP_B16_IRQ 0x30
+#define GPP_B17_IRQ 0x31
+#define GPP_B18_IRQ 0x32
+#define GPP_B19_IRQ 0x33
+#define GPP_B20_IRQ 0x34
+#define GPP_B21_IRQ 0x35
+#define GPP_B22_IRQ 0x36
+#define GPP_B23_IRQ 0x37
+
+/* Group A */
+#define GPP_A0_IRQ 0x38
+#define GPP_A1_IRQ 0x39
+#define GPP_A2_IRQ 0x3a
+#define GPP_A3_IRQ 0x3b
+#define GPP_A4_IRQ 0x3c
+#define GPP_A5_IRQ 0x3d
+#define GPP_A6_IRQ 0x3e
+#define GPP_A7_IRQ 0x3f
+#define GPP_A8_IRQ 0x40
+#define GPP_A9_IRQ 0x41
+#define GPP_A10_IRQ 0x42
+#define GPP_A11_IRQ 0x43
+#define GPP_A12_IRQ 0x44
+#define GPP_A13_IRQ 0x45
+#define GPP_A14_IRQ 0x46
+#define GPP_A15_IRQ 0x47
+#define GPP_A16_IRQ 0x48
+#define GPP_A17_IRQ 0x49
+#define GPP_A18_IRQ 0x4a
+#define GPP_A19_IRQ 0x4b
+
+/* Group H */
+#define GPP_H0_IRQ 0x70
+#define GPP_H1_IRQ 0x71
+#define GPP_H2_IRQ 0x72
+#define GPP_H3_IRQ 0x73
+#define GPP_H4_IRQ 0x74
+#define GPP_H5_IRQ 0x75
+#define GPP_H6_IRQ 0x76
+#define GPP_H7_IRQ 0x77
+#define GPP_H8_IRQ 0x18
+#define GPP_H9_IRQ 0x19
+#define GPP_H10_IRQ 0x1a
+#define GPP_H11_IRQ 0x1b
+#define GPP_H12_IRQ 0x1c
+#define GPP_H13_IRQ 0x1d
+#define GPP_H14_IRQ 0x1e
+#define GPP_H15_IRQ 0x1f
+#define GPP_H16_IRQ 0x20
+#define GPP_H17_IRQ 0x21
+#define GPP_H18_IRQ 0x22
+#define GPP_H19_IRQ 0x23
+#define GPP_H20_IRQ 0x24
+#define GPP_H21_IRQ 0x25
+#define GPP_H22_IRQ 0x26
+#define GPP_H23_IRQ 0x27
+
+/* Group D */
+#define GPP_D0_IRQ 0x28
+#define GPP_D1_IRQ 0x29
+#define GPP_D2_IRQ 0x2a
+#define GPP_D3_IRQ 0x2b
+#define GPP_D4_IRQ 0x2c
+#define GPP_D5_IRQ 0x2d
+#define GPP_D6_IRQ 0x2e
+#define GPP_D7_IRQ 0x2f
+#define GPP_D8_IRQ 0x30
+#define GPP_D9_IRQ 0x31
+#define GPP_D10_IRQ 0x32
+#define GPP_D11_IRQ 0x33
+#define GPP_D12_IRQ 0x34
+#define GPP_D13_IRQ 0x35
+#define GPP_D14_IRQ 0x36
+#define GPP_D15_IRQ 0x37
+#define GPP_D16_IRQ 0x38
+#define GPP_D17_IRQ 0x39
+#define GPP_D18_IRQ 0x3a
+#define GPP_D19_IRQ 0x3b
+#define GPP_D20_IRQ 0x3c
+#define GPP_D21_IRQ 0x3d
+#define GPP_D22_IRQ 0x3e
+#define GPP_D23_IRQ 0x3f
+
+/* Group GPD */
+#define GPD0_IRQ 0x64
+#define GPD1_IRQ 0x65
+#define GPD2_IRQ 0x66
+#define GPD3_IRQ 0x67
+#define GPD4_IRQ 0x68
+#define GPD5_IRQ 0x69
+#define GPD6_IRQ 0x6a
+#define GPD7_IRQ 0x6b
+#define GPD8_IRQ 0x6c
+#define GPD9_IRQ 0x6d
+#define GPD10_IRQ 0x6e
+
+/* Group C */
+#define GPP_C0_IRQ 0x5a
+#define GPP_C1_IRQ 0x5b
+#define GPP_C2_IRQ 0x5c
+#define GPP_C3_IRQ 0x5d
+#define GPP_C4_IRQ 0x5e
+#define GPP_C5_IRQ 0x5f
+#define GPP_C6_IRQ 0x60
+#define GPP_C7_IRQ 0x61
+#define GPP_C8_IRQ 0x62
+#define GPP_C9_IRQ 0x63
+#define GPP_C10_IRQ 0x64
+#define GPP_C11_IRQ 0x65
+#define GPP_C12_IRQ 0x66
+#define GPP_C13_IRQ 0x67
+#define GPP_C14_IRQ 0x68
+#define GPP_C15_IRQ 0x69
+#define GPP_C16_IRQ 0x6a
+#define GPP_C17_IRQ 0x6b
+#define GPP_C18_IRQ 0x6c
+#define GPP_C19_IRQ 0x6d
+#define GPP_C20_IRQ 0x6e
+#define GPP_C21_IRQ 0x6f
+#define GPP_C22_IRQ 0x70
+#define GPP_C23_IRQ 0x71
+/* Group E */
+#define GPP_E0_IRQ 0x72
+#define GPP_E1_IRQ 0x73
+#define GPP_E2_IRQ 0x74
+#define GPP_E3_IRQ 0x75
+#define GPP_E4_IRQ 0x76
+#define GPP_E5_IRQ 0x77
+#define GPP_E6_IRQ 0x18
+#define GPP_E7_IRQ 0x19
+#define GPP_E8_IRQ 0x1a
+#define GPP_E9_IRQ 0x1b
+#define GPP_E10_IRQ 0x1c
+#define GPP_E11_IRQ 0x1d
+#define GPP_E12_IRQ 0x1e
+#define GPP_E13_IRQ 0x1f
+#define GPP_E14_IRQ 0x20
+#define GPP_E15_IRQ 0x21
+#define GPP_E16_IRQ 0x22
+#define GPP_E17_IRQ 0x23
+#define GPP_E18_IRQ 0x24
+#define GPP_E19_IRQ 0x25
+#define GPP_E20_IRQ 0x26
+#define GPP_E21_IRQ 0x27
+#define GPP_E22_IRQ 0x28
+#define GPP_E23_IRQ 0x29
+
+/* Group R*/
+#define GPP_R0_IRQ 0x50
+#define GPP_R1_IRQ 0x51
+#define GPP_R2_IRQ 0x52
+#define GPP_R3_IRQ 0x53
+#define GPP_R4_IRQ 0x54
+#define GPP_R5_IRQ 0x55
+#define GPP_R6_IRQ 0x56
+#define GPP_R7_IRQ 0x57
+
+/* Group S */
+#define GPP_S0_IRQ 0x5c
+#define GPP_S1_IRQ 0x5d
+#define GPP_S2_IRQ 0x5e
+#define GPP_S3_IRQ 0x5f
+#define GPP_S4_IRQ 0x60
+#define GPP_S5_IRQ 0x61
+#define GPP_S6_IRQ 0x62
+#define GPP_S7_IRQ 0x63
+
+/* Register defines. */
+#define GPIO_MISCCFG 0x10
+#define GPE_DW_SHIFT 8
+#define GPE_DW_MASK 0xfff00
+#define HOSTSW_OWN_REG_0 0xc0
+#define GPI_INT_STS_0 0x100
+#define GPI_INT_EN_0 0x120
+#define GPI_SMI_STS_0 0x180
+#define GPI_SMI_EN_0 0x1a0
+#define PAD_CFG_BASE 0x600
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h b/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h
new file mode 100644
index 0000000000..35a15ded66
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h
@@ -0,0 +1,314 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_
+#define _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_
+
+#ifndef __ACPI__
+#include <stddef.h>
+#endif
+#include <soc/gpio_soc_defs.h>
+
+#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
+
+#define NUM_GPIO_COMx_GPI_REGS(n) \
+ (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
+#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
+#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
+
+#define NUM_GPI_STATUS_REGS \
+ ((NUM_GPIO_COM0_GPI_REGS) +\
+ (NUM_GPIO_COM1_GPI_REGS) +\
+ (NUM_GPIO_COM2_GPI_REGS) +\
+ (NUM_GPIO_COM4_GPI_REGS) +\
+ (NUM_GPIO_COM5_GPI_REGS))
+/*
+ * IOxAPIC IRQs for the GPIOs
+ */
+
+/* Group B */
+#define GPP_B0_IRQ 0x18
+#define GPP_B1_IRQ 0x19
+#define GPP_B2_IRQ 0x1A
+#define GPP_B3_IRQ 0x1B
+#define GPP_B4_IRQ 0x1C
+#define GPP_B5_IRQ 0x1D
+#define GPP_B6_IRQ 0x1E
+#define GPP_B7_IRQ 0x1F
+#define GPP_B8_IRQ 0x20
+#define GPP_B9_IRQ 0x21
+#define GPP_B10_IRQ 0x22
+#define GPP_B11_IRQ 0x23
+#define GPP_B12_IRQ 0x24
+#define GPP_B13_IRQ 0x25
+#define GPP_B14_IRQ 0x26
+#define GPP_B15_IRQ 0x27
+#define GPP_B16_IRQ 0x28
+#define GPP_B17_IRQ 0x29
+#define GPP_B18_IRQ 0x2A
+#define GPP_B19_IRQ 0x2B
+#define GPP_B20_IRQ 0x2C
+#define GPP_B21_IRQ 0x2D
+#define GPP_B22_IRQ 0x2E
+#define GPP_B23_IRQ 0x2F
+
+/* Group T */
+#define GPP_T0_IRQ 0x30
+#define GPP_T1_IRQ 0x31
+#define GPP_T2_IRQ 0x32
+#define GPP_T3_IRQ 0x33
+#define GPP_T4_IRQ 0x34
+#define GPP_T5_IRQ 0x35
+#define GPP_T6_IRQ 0x36
+#define GPP_T7_IRQ 0x37
+#define GPP_T8_IRQ 0x38
+#define GPP_T9_IRQ 0x39
+#define GPP_T10_IRQ 0x3A
+#define GPP_T11IRQ 0x3B
+#define GPP_T12_IRQ 0x3C
+#define GPP_T13_IRQ 0x3D
+#define GPP_T14_IRQ 0x3E
+#define GPP_T15_IRQ 0x3F
+
+/* Group A */
+#define GPP_A0_IRQ 0x40
+#define GPP_A1_IRQ 0x41
+#define GPP_A2_IRQ 0x42
+#define GPP_A3_IRQ 0x43
+#define GPP_A4_IRQ 0x44
+#define GPP_A5_IRQ 0x45
+#define GPP_A6_IRQ 0x46
+#define GPP_A7_IRQ 0x47
+#define GPP_A8_IRQ 0x48
+#define GPP_A9_IRQ 0x49
+#define GPP_A10_IRQ 0x4A
+#define GPP_A11_IRQ 0x4B
+#define GPP_A12_IRQ 0x4C
+#define GPP_A13_IRQ 0x4D
+#define GPP_A14_IRQ 0x4E
+#define GPP_A15_IRQ 0x4F
+#define GPP_A16_IRQ 0x50
+#define GPP_A17_IRQ 0x51
+#define GPP_A18_IRQ 0x52
+#define GPP_A19_IRQ 0x53
+#define GPP_A20_IRQ 0x54
+#define GPP_A21_IRQ 0x55
+#define GPP_A22_IRQ 0x56
+#define GPP_A23_IRQ 0x57
+
+/* Group R */
+#define GPP_R0_IRQ 0x58
+#define GPP_R1_IRQ 0x59
+#define GPP_R2_IRQ 0x5A
+#define GPP_R3_IRQ 0x5B
+#define GPP_R4_IRQ 0x5C
+#define GPP_R5_IRQ 0x5D
+#define GPP_R6_IRQ 0x5E
+#define GPP_R7_IRQ 0x5F
+
+
+/* Group D */
+#define GPD0_IRQ 0x60
+#define GPD1_IRQ 0x61
+#define GPD2_IRQ 0x62
+#define GPD3_IRQ 0x63
+#define GPD4_IRQ 0x64
+#define GPD5_IRQ 0x65
+#define GPD6_IRQ 0x66
+#define GPD7_IRQ 0x67
+#define GPD8_IRQ 0x68
+#define GPD9_IRQ 0x69
+#define GPD10_IRQ 0x6A
+#define GPD11_IRQ 0x6B
+
+/* Group S */
+#define GPP_S0_IRQ 0x6C
+#define GPP_S1_IRQ 0x6D
+#define GPP_S2_IRQ 0x6E
+#define GPP_S3_IRQ 0x6F
+#define GPP_S4_IRQ 0x70
+#define GPP_S5_IRQ 0x71
+#define GPP_S6_IRQ 0x72
+#define GPP_S7_IRQ 0x73
+
+/* Group H */
+#define GPP_H0_IRQ 0x74
+#define GPP_H1_IRQ 0x75
+#define GPP_H2_IRQ 0x76
+#define GPP_H3_IRQ 0x77
+#define GPP_H4_IRQ 0x18
+#define GPP_H5_IRQ 0x19
+#define GPP_H6_IRQ 0x1A
+#define GPP_H7_IRQ 0x1B
+#define GPP_H8_IRQ 0x1C
+#define GPP_H9_IRQ 0x1D
+#define GPP_H10_IRQ 0x1E
+#define GPP_H11_IRQ 0x1F
+#define GPP_H12_IRQ 0x20
+#define GPP_H13_IRQ 0x21
+#define GPP_H14_IRQ 0x22
+#define GPP_H15_IRQ 0x23
+#define GPP_H16_IRQ 0x24
+#define GPP_H17_IRQ 0x25
+#define GPP_H18_IRQ 0x26
+#define GPP_H19_IRQ 0x27
+#define GPP_H20_IRQ 0x28
+#define GPP_H21_IRQ 0x29
+#define GPP_H22_IRQ 0x2A
+#define GPP_H23_IRQ 0x2B
+
+/* Group D */
+#define GPP_D0_IRQ 0x2C
+#define GPP_D1_IRQ 0x2D
+#define GPP_D2_IRQ 0x2E
+#define GPP_D3_IRQ 0x2F
+#define GPP_D4_IRQ 0x30
+#define GPP_D5_IRQ 0x31
+#define GPP_D6_IRQ 0x32
+#define GPP_D7_IRQ 0x33
+#define GPP_D8_IRQ 0x34
+#define GPP_D9_IRQ 0x35
+#define GPP_D10_IRQ 0x36
+#define GPP_D11_IRQ 0x37
+#define GPP_D12_IRQ 0x38
+#define GPP_D13_IRQ 0x39
+#define GPP_D14_IRQ 0x3A
+#define GPP_D15_IRQ 0x3B
+#define GPP_D16_IRQ 0x3C
+#define GPP_D17_IRQ 0x3D
+#define GPP_D18_IRQ 0x3E
+#define GPP_D19_IRQ 0x3F
+
+
+/* Group U */
+#define GPP_U0_IRQ 0x40
+#define GPP_U1IRQ 0x41
+#define GPP_U2_IRQ 0x42
+#define GPP_U3_IRQ 0x43
+#define GPP_U4_IRQ 0x44
+#define GPP_U5_IRQ 0x45
+#define GPP_U6_IRQ 0x46
+#define GPP_U7_IRQ 0x47
+#define GPP_U8_IRQ 0x48
+#define GPP_U9_IRQ 0x49
+#define GPP_U10_IRQ 0x4A
+#define GPP_U11_IRQ 0x4B
+#define GPP_U12_IRQ 0x4C
+#define GPP_U13_IRQ 0x4D
+#define GPP_U14_IRQ 0x4E
+#define GPP_U15_IRQ 0x4F
+#define GPP_U16_IRQ 0x50
+#define GPP_U17_IRQ 0x51
+#define GPP_U18_IRQ 0x52
+#define GPP_U19_IRQ 0x53
+
+
+#define GPP_VGPIO4_IRQ 0x54
+
+/* Group F */
+#define GPP_F0_IRQ 0x56
+#define GPP_F1_IRQ 0x57
+#define GPP_F2_IRQ 0x58
+#define GPP_F3_IRQ 0x59
+#define GPP_F4_IRQ 0x5A
+#define GPP_F5_IRQ 0x5B
+#define GPP_F6_IRQ 0x5C
+#define GPP_F7_IRQ 0x5D
+#define GPP_F8_IRQ 0x5E
+#define GPP_F9_IRQ 0x5F
+#define GPP_F10_IRQ 0x60
+#define GPP_F11_IRQ 0x61
+#define GPP_F12_IRQ 0x62
+#define GPP_F13_IRQ 0x63
+#define GPP_F14_IRQ 0x64
+#define GPP_F15_IRQ 0x65
+#define GPP_F16_IRQ 0x66
+#define GPP_F17_IRQ 0x67
+#define GPP_F18_IRQ 0x68
+#define GPP_F19_IRQ 0x69
+#define GPP_F20_IRQ 0x6A
+#define GPP_F21_IRQ 0x6B
+#define GPP_F22_IRQ 0x6C
+#define GPP_F23_IRQ 0x6D
+
+/* Group C */
+#define GPP_C0_iIRQ 0x6E
+#define GPP_C1_IRQ 0x6F
+#define GPP_C2_IRQ 0x70
+#define GPP_C3_IRQ 0x71
+#define GPP_C4_IRQ 0x72
+#define GPP_C5_IRQ 0x73
+#define GPP_C6_IRQ 0x74
+#define GPP_C7_IRQ 0x75
+#define GPP_C8_IRQ 0x76
+#define GPP_C9_IRQ 0x77
+#define GPP_C10_IRQ 0x18
+#define GPP_C11_IRQ 0x19
+#define GPP_C12_IRQ 0x1A
+#define GPP_C13_IRQ 0x1B
+#define GPP_C14_IRQ 0x1C
+#define GPP_C15_IRQ 0x1D
+#define GPP_C16_IRQ 0x1E
+#define GPP_C17_IRQ 0x1F
+#define GPP_C18_IRQ 0x20
+#define GPP_C19_IRQ 0x21
+#define GPP_C20_IRQ 0x22
+#define GPP_C21_IRQ 0x23
+#define GPP_C22_IRQ 0x24
+#define GPP_C23_IRQ 0x25
+
+
+
+/* Group E */
+#define GPP_E0_IRQ 0x26
+#define GPP_E1_IRQ 0x27
+#define GPP_E2_IRQ 0x28
+#define GPP_E3_IRQ 0x29
+#define GPP_E4_IRQ 0x30
+#define GPP_E5_IRQ 0x31
+#define GPP_E6_IRQ 0x32
+#define GPP_E7_IRQ 0x33
+#define GPP_E8_IRQ 0x34
+#define GPP_E9_IRQ 0x35
+#define GPP_E10_IRQ 0x36
+#define GPP_E11_IRQ 0x37
+#define GPP_E12_IRQ 0x38
+#define GPP_E13_IRQ 0x39
+#define GPP_E14_IRQ 0x3A
+#define GPP_E15_IRQ 0x3B
+#define GPP_E16_IRQ 0x3C
+#define GPP_E17_IRQ 0x3D
+#define GPP_E18_IRQ 0x3E
+#define GPP_E19_IRQ 0x3F
+#define GPP_E20_IRQ 0x40
+#define GPP_E21_IRQ 0x41
+#define GPP_E22_IRQ 0x42
+#define GPP_E23_IRQ 0x43
+
+/* Register defines. */
+#define GPIO_MISCCFG 0x10
+#define GPE_DW_SHIFT 8
+#define GPE_DW_MASK 0xfff00
+#define HOSTSW_OWN_REG_0 0xb0
+#define GPI_INT_STS_0 0x100
+#define GPI_INT_EN_0 0x110
+#define GPI_SMI_STS_0 0x180
+#define GPI_SMI_EN_0 0x1A0
+#define PAD_CFG_BASE 0x700
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h
new file mode 100644
index 0000000000..b3ab9c3b5b
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_
+#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
+ #include "gpio_soc_defs_tgl.h"
+#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY)
+ #include "gpio_soc_defs_jsl.h"
+#endif
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h
new file mode 100644
index 0000000000..2ee52b260f
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h
@@ -0,0 +1,358 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_
+#define _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_
+
+/*
+ * Most of the fixed numbers and macros are based on the GPP groups.
+ * The GPIO groups are accessed through register blocks called
+ * communities.
+ */
+
+#define GPP_A 0x0
+#define GPP_B 0x1
+#define GPP_G 0x2
+#define GPP_C 0x3
+#define GPP_R 0x4
+#define GPP_D 0x5
+#define GPP_S 0x6
+#define GPP_H 0x7
+#define GPP_VGPIO 0x8
+#define GPP_F 0x9
+#define GPP_GPD 0xA
+#define GPP_E 0xD
+
+#define GPIO_NUM_GROUPS 12
+#define GPIO_MAX_NUM_PER_GROUP 24
+
+/*
+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
+ */
+
+/* Group F */
+#define GPP_F0 0
+#define GPP_F1 1
+#define GPP_F2 2
+#define GPP_F3 3
+#define GPP_F4 4
+#define GPP_F5 5
+#define GPP_F6 6
+#define GPP_F7 7
+#define GPP_F8 8
+#define GPP_F9 9
+#define GPP_F10 10
+#define GPP_F11 11
+#define GPP_F12 12
+#define GPP_F13 13
+#define GPP_F14 14
+#define GPP_F15 15
+#define GPP_F16 16
+#define GPP_F17 17
+#define GPP_F18 18
+#define GPP_F19 19
+
+/* Group B */
+#define GPIO_RSVD_0 20
+#define GPIO_RSVD_1 21
+#define GPIO_RSVD_2 22
+#define GPIO_RSVD_3 23
+#define GPIO_RSVD_4 24
+#define GPIO_RSVD_5 25
+#define GPIO_RSVD_6 26
+#define GPIO_RSVD_7 27
+#define GPIO_RSVD_8 28
+#define GPP_B0 29
+#define GPP_B1 30
+#define GPP_B2 31
+#define GPP_B3 32
+#define GPP_B4 33
+#define GPP_B5 34
+#define GPP_B6 35
+#define GPP_B7 36
+#define GPP_B8 37
+#define GPP_B9 38
+#define GPP_B10 39
+#define GPP_B11 40
+#define GPP_B12 41
+#define GPP_B13 42
+#define GPP_B14 43
+#define GPP_B15 44
+#define GPP_B16 45
+#define GPP_B17 46
+#define GPP_B18 47
+#define GPP_B19 48
+#define GPP_B20 49
+#define GPP_B21 50
+#define GPP_B22 51
+#define GPP_B23 52
+#define GPIO_RSVD_9 53
+#define GPIO_RSVD_10 54
+
+/* Group A */
+#define GPP_A0 55
+#define GPP_A1 56
+#define GPP_A2 57
+#define GPP_A3 58
+#define GPP_A4 59
+#define GPP_A5 60
+#define GPP_A6 61
+#define GPP_A7 62
+#define GPP_A8 63
+#define GPP_A9 64
+#define GPP_A10 65
+#define GPP_A11 66
+#define GPP_A12 67
+#define GPP_A13 68
+#define GPP_A14 69
+#define GPP_A15 70
+#define GPP_A16 71
+#define GPP_A17 72
+#define GPP_A18 73
+#define GPP_A19 74
+#define GPIO_RSVD_11 75
+
+/* Group S */
+#define GPP_S0 76
+#define GPP_S1 77
+#define GPP_S2 78
+#define GPP_S3 79
+#define GPP_S4 80
+#define GPP_S5 81
+#define GPP_S6 82
+#define GPP_S7 83
+
+/* Group R */
+#define GPP_R0 84
+#define GPP_R1 85
+#define GPP_R2 86
+#define GPP_R3 87
+#define GPP_R4 88
+#define GPP_R5 89
+#define GPP_R6 90
+#define GPP_R7 91
+
+#define GPIO_COM0_START GPP_F0
+#define GPIO_COM0_END GPP_R7
+#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1)
+
+/* Group H */
+#define GPP_H0 92
+#define GPP_H1 93
+#define GPP_H2 94
+#define GPP_H3 95
+#define GPP_H4 96
+#define GPP_H5 97
+#define GPP_H6 98
+#define GPP_H7 99
+#define GPP_H8 100
+#define GPP_H9 101
+#define GPP_H10 102
+#define GPP_H11 103
+#define GPP_H12 104
+#define GPP_H13 105
+#define GPP_H14 106
+#define GPP_H15 107
+#define GPP_H16 108
+#define GPP_H17 109
+#define GPP_H18 110
+#define GPP_H19 111
+#define GPP_H20 112
+#define GPP_H21 113
+#define GPP_H22 114
+#define GPP_H23 115
+
+/* Group D */
+#define GPP_D0 116
+#define GPP_D1 117
+#define GPP_D2 118
+#define GPP_D3 119
+#define GPP_D4 120
+#define GPP_D5 121
+#define GPP_D6 122
+#define GPP_D7 123
+#define GPP_D8 124
+#define GPP_D9 125
+#define GPP_D10 126
+#define GPP_D11 127
+#define GPP_D12 128
+#define GPP_D13 129
+#define GPP_D14 130
+#define GPP_D15 131
+#define GPP_D16 132
+#define GPP_D17 133
+#define GPP_D18 134
+#define GPP_D19 135
+#define GPP_D20 136
+#define GPP_D21 137
+#define GPP_D22 138
+#define GPP_D23 139
+#define GPIO_RSVD_12 140
+#define GPIO_RSVD_13 141
+
+/* Group VGPIO */
+#define VGPIO_0 142
+#define VGPIO_3 143
+#define VGPIO_4 144
+#define VGPIO_5 145
+#define VGPIO_6 146
+#define VGPIO_7 147
+#define VGPIO_8 148
+#define VGPIO_9 149
+#define VGPIO_10 150
+#define VGPIO_11 151
+#define VGPIO_12 152
+#define VGPIO_13 153
+#define VGPIO_18 154
+#define VGPIO_19 155
+#define VGPIO_20 156
+#define VGPIO_21 157
+#define VGPIO_22 158
+#define VGPIO_23 159
+#define VGPIO_24 160
+#define VGPIO_25 161
+#define VGPIO_30 162
+#define VGPIO_31 163
+#define VGPIO_32 164
+#define VGPIO_33 165
+#define VGPIO_34 166
+#define VGPIO_35 167
+#define VGPIO_36 168
+#define VGPIO_37 169
+#define VGPIO_39 170
+
+/* Group C */
+#define GPP_C0 171
+#define GPP_C1 172
+#define GPP_C2 173
+#define GPP_C3 174
+#define GPP_C4 175
+#define GPP_C5 176
+#define GPP_C6 177
+#define GPP_C7 178
+#define GPP_C8 179
+#define GPP_C9 180
+#define GPP_C10 181
+#define GPP_C11 182
+#define GPP_C12 183
+#define GPP_C13 184
+#define GPP_C14 185
+#define GPP_C15 186
+#define GPP_C16 187
+#define GPP_C17 188
+#define GPP_C18 189
+#define GPP_C19 190
+#define GPP_C20 191
+#define GPP_C21 192
+#define GPP_C22 193
+#define GPP_C23 194
+
+#define GPIO_COM1_START GPP_H0
+#define GPIO_COM1_END GPP_C23
+#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1)
+
+/* Group GPD */
+#define GPD0 195
+#define GPD1 196
+#define GPD2 197
+#define GPD3 198
+#define GPD4 199
+#define GPD5 200
+#define GPD6 201
+#define GPD7 202
+#define GPD8 203
+#define GPD9 204
+#define GPD10 205
+#define GPIO_RSVD_14 206
+#define GPIO_RSVD_15 207
+#define GPIO_RSVD_16 208
+#define GPIO_RSVD_17 209
+
+#define GPIO_COM2_START GPD0
+#define GPIO_COM2_END GPIO_RSVD_17
+#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1)
+
+/* Group E */
+#define GPIO_RSVD_18 210
+#define GPIO_RSVD_19 211
+#define GPIO_RSVD_20 212
+#define GPIO_RSVD_21 213
+#define GPIO_RSVD_22 214
+#define GPIO_RSVD_23 215
+#define GPP_E0 216
+#define GPP_E1 217
+#define GPP_E2 218
+#define GPP_E3 219
+#define GPP_E4 220
+#define GPP_E5 221
+#define GPP_E6 222
+#define GPP_E7 223
+#define GPP_E8 224
+#define GPP_E9 225
+#define GPP_E10 226
+#define GPP_E11 227
+#define GPP_E12 228
+#define GPP_E13 229
+#define GPP_E14 230
+#define GPP_E15 231
+#define GPP_E16 232
+#define GPP_E17 233
+#define GPP_E18 234
+#define GPP_E19 235
+#define GPP_E20 236
+#define GPP_E21 237
+#define GPP_E22 238
+#define GPP_E23 239
+#define GPIO_RSVD_24 240
+#define GPIO_RSVD_25 241
+#define GPIO_RSVD_26 242
+#define GPIO_RSVD_27 243
+#define GPIO_RSVD_28 244
+#define GPIO_RSVD_29 245
+#define GPIO_RSVD_30 246
+#define GPIO_RSVD_31 247
+#define GPIO_RSVD_32 248
+#define GPIO_RSVD_33 249
+#define GPIO_RSVD_34 250
+#define GPIO_RSVD_35 251
+#define GPIO_RSVD_36 252
+
+#define GPIO_COM4_START GPIO_RSVD_18
+#define GPIO_COM4_END GPIO_RSVD_36
+#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1)
+
+/* Group G */
+#define GPP_G0 253
+#define GPP_G1 254
+#define GPP_G2 255
+#define GPP_G3 256
+#define GPP_G4 257
+#define GPP_G5 258
+#define GPP_G6 259
+#define GPP_G7 260
+
+#define GPIO_COM5_START GPP_G0
+#define GPIO_COM5_END GPP_G7
+#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1)
+
+#define TOTAL_PADS 261
+
+#define COMM_0 0
+#define COMM_1 1
+#define COMM_2 2
+#define COMM_4 3
+#define COMM_5 4
+#define TOTAL_GPIO_COMM 5
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h
new file mode 100644
index 0000000000..ec582c3133
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h
@@ -0,0 +1,394 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_
+#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_
+/*
+ * Most of the fixed numbers and macros are based on the GPP groups.
+ * The GPIO groups are accessed through register blocks called
+ * communities.
+ */
+#define GPP_B 0x0
+#define GPP_T 0x1
+#define GPP_A 0x2
+#define GPP_R 0x3
+#define GPD 0x4
+#define GPP_S 0x5
+#define GPP_H 0x6
+#define GPP_D 0x7
+#define GPP_U 0x8
+#define GPP_F 0xA
+#define GPP_C 0xB
+#define GPP_E 0xC
+
+#define GPIO_MAX_NUM_PER_GROUP 27
+
+#define COMM_0 0
+#define COMM_1 1
+#define COMM_2 2
+/* GPIO community 3 is not exposed to be used and hence is skipped. */
+#define COMM_4 3
+#define COMM_5 4
+/*
+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
+ */
+/* Group B */
+#define GPP_B0 0
+#define GPP_B1 1
+#define GPP_B2 2
+#define GPP_B3 3
+#define GPP_B4 4
+#define GPP_B5 5
+#define GPP_B6 6
+#define GPP_B7 7
+#define GPP_B8 8
+#define GPP_B9 9
+#define GPP_B10 10
+#define GPP_B11 11
+#define GPP_B12 12
+#define GPP_B13 13
+#define GPP_B14 14
+#define GPP_B15 15
+#define GPP_B16 16
+#define GPP_B17 17
+#define GPP_B18 18
+#define GPP_B19 19
+#define GPP_B20 20
+#define GPP_B21 21
+#define GPP_B22 22
+#define GPP_B23 23
+#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */
+#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */
+
+/* Group T */
+#define GPP_T0 26
+#define GPP_T1 27
+#define GPP_T2 28
+#define GPP_T3 29
+#define GPP_T4 30
+#define GPP_T5 31
+#define GPP_T6 32
+#define GPP_T7 33
+#define GPP_T8 34
+#define GPP_T9 35
+#define GPP_T10 36
+#define GPP_T11 37
+#define GPP_T12 38
+#define GPP_T13 39
+#define GPP_T14 40
+#define GPP_T15 41
+
+/* Group A */
+#define GPP_A0 42
+#define GPP_A1 43
+#define GPP_A2 44
+#define GPP_A3 45
+#define GPP_A4 46
+#define GPP_A5 47
+#define GPP_A6 48
+#define GPP_A7 49
+#define GPP_A8 50
+#define GPP_A9 51
+#define GPP_A10 52
+#define GPP_A11 53
+#define GPP_A12 54
+#define GPP_A13 55
+#define GPP_A14 56
+#define GPP_A15 57
+#define GPP_A16 58
+#define GPP_A17 59
+#define GPP_A18 60
+#define GPP_A19 61
+#define GPP_A20 62
+#define GPP_A21 63
+#define GPP_A22 64
+#define GPP_A23 65
+#define GPP_A24 66 /* ESPI_CLK_LOOPBK */
+
+#define GPIO_COM0_START GPP_B0
+#define GPIO_COM0_END GPP_A24
+#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1)
+
+/* Group S */
+#define GPP_S0 67
+#define GPP_S1 68
+#define GPP_S2 69
+#define GPP_S3 70
+#define GPP_S4 71
+#define GPP_S5 72
+#define GPP_S6 73
+#define GPP_S7 74
+
+/* Group H */
+#define GPP_H0 75
+#define GPP_H1 76
+#define GPP_H2 77
+#define GPP_H3 78
+#define GPP_H4 79
+#define GPP_H5 80
+#define GPP_H6 81
+#define GPP_H7 82
+#define GPP_H8 83
+#define GPP_H9 84
+#define GPP_H10 85
+#define GPP_H11 86
+#define GPP_H12 87
+#define GPP_H13 88
+#define GPP_H14 89
+#define GPP_H15 90
+#define GPP_H16 91
+#define GPP_H17 92
+#define GPP_H18 93
+#define GPP_H19 94
+#define GPP_H20 95
+#define GPP_H21 96
+#define GPP_H22 97
+#define GPP_H23 98
+
+/* Group D */
+#define GPP_D0 99
+#define GPP_D1 100
+#define GPP_D2 101
+#define GPP_D3 102
+#define GPP_D4 103
+#define GPP_D5 104
+#define GPP_D6 105
+#define GPP_D7 106
+#define GPP_D8 107
+#define GPP_D9 108
+#define GPP_D10 109
+#define GPP_D11 110
+#define GPP_D12 111
+#define GPP_D13 112
+#define GPP_D14 113
+#define GPP_D15 114
+#define GPP_D16 115
+#define GPP_D17 116
+#define GPP_D18 117
+#define GPP_D19 118
+#define GPP_GSPI2_CLK_LOOPBK 119
+
+/* Group U */
+#define GPP_U0 120
+#define GPP_U1 121
+#define GPP_U2 122
+#define GPP_U3 123
+#define GPP_U4 124
+#define GPP_U5 125
+#define GPP_U6 126
+#define GPP_U7 127
+#define GPP_U8 128
+#define GPP_U9 129
+#define GPP_U10 130
+#define GPP_U11 131
+#define GPP_U12 132
+#define GPP_U13 133
+#define GPP_U14 134
+#define GPP_U15 135
+#define GPP_U16 136
+#define GPP_U17 137
+#define GPP_U18 138
+#define GPP_U19 139
+#define GPP_GSPI3_CLK_LOOPBK 140
+#define GPP_GSPI4_CLK_LOOPBK 141
+#define GPP_GSPI5_CLK_LOOPBK 142
+#define GPP_GSPI6_CLK_LOOPBK 143
+
+/* Group VGPIO */
+#define CNV_BTEN 144
+#define CNV_BT_HOST_WAKEB 145
+#define CNV_BT_IF_SELECT 146
+#define vCNV_BT_UART_TXD 147
+#define vCNV_BT_UART_RXD 148
+#define vCNV_BT_UART_CTS_B 149
+#define vCNV_BT_UART_RTS_B 150
+#define vCNV_MFUART1_TXD 151
+#define vCNV_MFUART1_RXD 152
+#define vCNV_MFUART1_CTS_B 153
+#define vCNV_MFUART1_RTS_B 154
+#define vUART0_TXD 155
+#define vUART0_RXD 156
+#define vUART0_CTS_B 157
+#define vUART0_RTS_B 158
+#define vISH_UART0_TXD 159
+#define vISH_UART0_RXD 160
+#define vISH_UART0_CTS_B 161
+#define vISH_UART0_RTS_B 162
+#define vCNV_BT_I2S_BCLK 163
+#define vCNV_BT_I2S_WS_SYNC 164
+#define vCNV_BT_I2S_SDO 165
+#define vCNV_BT_I2S_SDI 166
+#define vI2S2_SCLK 167
+#define vI2S2_SFRM 168
+#define vI2S2_TXD 169
+#define vI2S2_RXD 170
+
+#define GPIO_COM1_START GPP_S0
+#define GPIO_COM1_END vI2S2_RXD
+#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1)
+
+/* Group GPD */
+#define GPD0 171
+#define GPD1 172
+#define GPD2 173
+#define GPD3 174
+#define GPD4 175
+#define GPD5 176
+#define GPD6 177
+#define GPD7 178
+#define GPD8 179
+#define GPD9 180
+#define GPD10 181
+#define GPD11 182
+#define GPD_INPUT3VSEL 183
+#define GPD_SLP_LANB 184
+#define GPD__SLP_SUSB 185
+#define GPD_WAKEB 186
+#define GPD_DRAM_RESETB 187
+
+#define GPIO_COM2_START GPD0
+#define GPIO_COM2_END GPD_DRAM_RESETB
+#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1)
+
+/* Group C */
+#define GPP_C0 188
+#define GPP_C1 189
+#define GPP_C2 190
+#define GPP_C3 191
+#define GPP_C4 192
+#define GPP_C5 193
+#define GPP_C6 194
+#define GPP_C7 195
+#define GPP_C8 196
+#define GPP_C9 197
+#define GPP_C10 198
+#define GPP_C11 199
+#define GPP_C12 200
+#define GPP_C13 201
+#define GPP_C14 202
+#define GPP_C15 203
+#define GPP_C16 204
+#define GPP_C17 205
+#define GPP_C18 206
+#define GPP_C19 207
+#define GPP_C20 208
+#define GPP_C21 209
+#define GPP_C22 210
+#define GPP_C23 211
+
+/* Group F */
+#define GPP_F0 212
+#define GPP_F1 213
+#define GPP_F2 214
+#define GPP_F3 215
+#define GPP_F4 216
+#define GPP_F5 217
+#define GPP_F6 218
+#define GPP_F7 219
+#define GPP_F8 220
+#define GPP_F9 221
+#define GPP_F10 222
+#define GPP_F11 223
+#define GPP_F12 224
+#define GPP_F13 225
+#define GPP_F14 226
+#define GPP_F15 227
+#define GPP_F16 228
+#define GPP_F17 229
+#define GPP_F18 230
+#define GPP_F19 231
+#define GPP_F20 232
+#define GPP_F21 233
+#define GPP_F22 234
+#define GPP_F23 235
+#define GPP_F_CLK_LOOPBK 236
+
+/* Group HVCMOS */
+#define GPP_L_BKLTEN 237
+#define GPP_L_BKLTCTL 238
+#define GPP_L_VDDEN 239
+#define GPP_SYS_PWROK 240
+#define GPP_SYS_RESETB 241
+#define GPP_MLK_RSTB 242
+
+/* Group E */
+#define GPP_E0 243
+#define GPP_E1 244
+#define GPP_E2 245
+#define GPP_E3 246
+#define GPP_E4 247
+#define GPP_E5 248
+#define GPP_E6 249
+#define GPP_E7 250
+#define GPP_E8 251
+#define GPP_E9 252
+#define GPP_E10 253
+#define GPP_E11 254
+#define GPP_E12 255
+#define GPP_E13 256
+#define GPP_E14 257
+#define GPP_E15 258
+#define GPP_E16 259
+#define GPP_E17 260
+#define GPP_E18 261
+#define GPP_E19 262
+#define GPP_E20 263
+#define GPP_E21 264
+#define GPP_E22 265
+#define GPP_E23 266
+#define GPP_E_CLK_LOOPBK 267
+
+/* Group JTAG */
+#define GPP_JTAG_TDO 268
+#define GPP_JTAG_X 269
+#define GPP_JTAG_PRDYB 270
+#define GPP_JTAG_PREQB 271
+#define GPP_CPU_TRSTB 272
+#define GPP_JTAG_TDI 273
+#define GPP_JTAG_TMS 274
+#define GPP_JTAG_TCK 275
+#define GPP_DBG_PMODE 276
+
+#define GPIO_COM4_START GPP_C0
+#define GPIO_COM4_END GPP_DBG_PMODE
+#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1)
+
+/* Group R */
+#define GPP_R0 277
+#define GPP_R1 278
+#define GPP_R2 279
+#define GPP_R3 280
+#define GPP_R4 281
+#define GPP_R5 282
+#define GPP_R6 283
+#define GPP_R7 284
+
+/* Group SPI */
+#define GPP_SPI_IO_2 285
+#define GPP_SPI_IO_3 286
+#define GPP_SPI_MOSI_IO_0 287
+#define GPP_SPI_MOSI_IO_1 288
+#define GPP_SPI_TPM_CSB 289
+#define GPP_SPI_FLASH_0_CSB 290
+#define GPP_SPI_FLASH_1_CSB 291
+#define GPP_SPI_CLK 292
+#define GPP_CLK_LOOPBK 293
+
+#define GPIO_COM5_START GPP_R0
+#define GPIO_COM5_END GPP_CLK_LOOPBK
+#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1)
+
+#define TOTAL_GPIO_COMM (COMM_5 + 1)
+#define TOTAL_PADS 294
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h
new file mode 100644
index 0000000000..5eda08a132
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/iomap.h
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Firmware Architecture Specification
+ * Document number: 608531
+ * Chapter number: 4
+ */
+
+#ifndef _SOC_TIGERLAKE_IOMAP_H_
+#define _SOC_TIGERLAKE_IOMAP_H_
+
+/*
+ * Memory-mapped I/O registers.
+ */
+#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+#define MCFG_BASE_SIZE 0x4000000
+
+#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
+#define PCH_PRESERVED_BASE_SIZE 0x02000000
+
+#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
+#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
+
+#define UART_BASE_SIZE 0x1000
+
+#define UART_BASE_0_ADDRESS 0xfe03e000
+/* Both UART BAR 0 and 1 are 4KB in size */
+#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \
+ UART_BASE_SIZE * (x)))
+#define UART_BASE(x) UART_BASE_0_ADDR(x)
+
+#define DMI_BASE_ADDRESS 0xfeda0000
+#define DMI_BASE_SIZE 0x1000
+
+#define EP_BASE_ADDRESS 0xfeda1000
+#define EP_BASE_SIZE 0x1000
+
+#define EDRAM_BASE_ADDRESS 0xfed80000
+#define EDRAM_BASE_SIZE 0x4000
+
+#define TBT0_BASE_ADDRESS 0xfed84000
+#define TBT0_BASE_SIZE 0x1000
+
+#define TBT1_BASE_ADDRESS 0xfed85000
+#define TBT1_BASE_SIZE 0x1000
+
+#define TBT2_BASE_ADDRESS 0xfed86000
+#define TBT2_BASE_SIZE 0x1000
+
+#define TBT3_BASE_ADDRESS 0xfed87000
+#define TBT3_BASE_SIZE 0x1000
+
+#define GFXVT_BASE_ADDRESS 0xfed90000
+#define GFXVT_BASE_SIZE 0x1000
+
+#define IPUVT_BASE_ADDRESS 0xfed92000
+#define IPUVT_BASE_SIZE 0x1000
+
+#define VTVC0_BASE_ADDRESS 0xfed91000
+#define VTVC0_BASE_SIZE 0x1000
+
+#define REG_BASE_ADDRESS 0xfb000000
+#define REG_BASE_SIZE 0x1000
+
+#define HPET_BASE_ADDRESS 0xfed00000
+
+#define PCH_PWRM_BASE_ADDRESS 0xfe000000
+#define PCH_PWRM_BASE_SIZE 0x10000
+
+#define SPI_BASE_ADDRESS 0xfe010000
+
+#define GPIO_BASE_SIZE 0x10000
+
+#define HECI1_BASE_ADDRESS 0xfeda2000
+
+#define VTD_BASE_ADDRESS 0xfed90000
+#define VTD_BASE_SIZE 0x00004000
+
+#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB)
+#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB)
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
+
+#define MCH_BASE_ADDRESS 0xfedc0000
+#define MCH_BASE_SIZE 0x20000
+
+#define EARLY_GSPI_BASE_ADDRESS 0xfe030000
+
+#define EARLY_I2C_BASE_ADDRESS 0xfe020000
+#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
+
+#else /* CONFIG_SOC_INTEL_JASPERLAKE_COPY */
+
+#define MCH_BASE_ADDRESS 0xfea80000
+#define MCH_BASE_SIZE 0x8000
+
+#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
+
+#define EARLY_I2C_BASE_ADDRESS 0xfe040000
+#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
+
+#endif
+
+/*
+ * I/O port address space
+ */
+#define SMBUS_BASE_ADDRESS 0x0efa0
+#define SMBUS_BASE_SIZE 0x20
+
+#define ACPI_BASE_ADDRESS 0x1800
+#define ACPI_BASE_SIZE 0x100
+
+#define TCO_BASE_ADDRESS 0x400
+#define TCO_BASE_SIZE 0x20
+
+#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
+#define P2SB_SIZE (16 * MiB)
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/irq.h b/src/soc/intel/jasperlake/include/soc/irq.h
new file mode 100644
index 0000000000..6ca2588a0d
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/irq.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_IRQ_H_
+#define _SOC_IRQ_H_
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
+ #include "irq_tgl.h"
+#else
+ #include "irq_jsl.h"
+#endif /* CONFIG_SOC_INTEL_TIGERLAKE_COPY */
+
+#endif /* _SOC_IRQ_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/irq_jsl.h b/src/soc/intel/jasperlake/include/soc/irq_jsl.h
new file mode 100644
index 0000000000..a6edd23d97
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/irq_jsl.h
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_JSL_IRQ_H_
+#define _SOC_JSL_IRQ_H_
+
+#define GPIO_IRQ14 14
+#define GPIO_IRQ15 15
+
+#define PCH_IRQ10 10
+#define PCH_IRQ11 11
+
+/* LPSS Devices */
+#define LPSS_I2C0_IRQ 16
+#define LPSS_I2C1_IRQ 17
+#define LPSS_I2C2_IRQ 18
+#define LPSS_I2C3_IRQ 19
+#define LPSS_I2C4_IRQ 32
+#define LPSS_I2C5_IRQ 33
+#define LPSS_SPI0_IRQ 22
+#define LPSS_SPI1_IRQ 23
+#define LPSS_SPI2_IRQ 24
+#define LPSS_UART0_IRQ 20
+#define LPSS_UART1_IRQ 21
+#define LPSS_UART2_IRQ 34
+
+/* PCI D:31 F:x */
+#define cAVS_INTA_IRQ 16
+#define SMBUS_INTA_IRQ 16
+#define SMBUS_INTB_IRQ 17
+#define GbE_INTA_IRQ 16
+#define GbE_INTC_IRQ 18
+#define TRACE_HUB_INTA_IRQ 16
+#define TRACE_HUB_INTD_IRQ 19
+
+/* PCI D:28 F:x */
+#define PCIE_1_IRQ 16
+#define PCIE_2_IRQ 17
+#define PCIE_3_IRQ 18
+#define PCIE_4_IRQ 19
+#define PCIE_5_IRQ 16
+#define PCIE_6_IRQ 17
+#define PCIE_7_IRQ 18
+#define PCIE_8_IRQ 19
+
+/* PCI D:26 F:x */
+#define eMMC_IRQ 16
+
+/* PCI D:23 F:x */
+#define SATA_IRQ 16
+
+/* PCI D:22 F:x */
+#define HECI_1_IRQ 16
+#define HECI_2_IRQ 17
+#define HECI_3_IRQ 16
+#define HECI_4_IRQ 19
+#define IDER_IRQ 18
+#define KT_IRQ 19
+
+/* PCI D:20 F:x */
+#define XHCI_IRQ 16
+#define OTG_IRQ 17
+#define CNViWIFI_IRQ 16
+#define SD_IRQ 19
+#define PMC_SRAM_IRQ 18
+
+/* PCI D:18 F:x */
+#define UFS_IRQ 16
+
+#define IGFX_IRQ 16
+#define SA_THERMAL_IRQ 16
+#define IPU_IRQ 16
+#define GNA_IRQ 16
+
+#endif /* _JSL_IRQ_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/irq_tgl.h b/src/soc/intel/jasperlake/include/soc/irq_tgl.h
new file mode 100644
index 0000000000..6f268c1eae
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/irq_tgl.h
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_TGL_IRQ_H_
+#define _SOC_TGL_IRQ_H_
+
+#define GPIO_IRQ14 14
+#define GPIO_IRQ15 15
+
+#define PCH_IRQ10 10
+#define PCH_IRQ11 11
+
+#define LPSS_I2C0_IRQ 27
+#define LPSS_I2C1_IRQ 28
+#define LPSS_I2C2_IRQ 29
+#define LPSS_I2C3_IRQ 30
+#define LPSS_I2C4_IRQ 31
+#define LPSS_I2C5_IRQ 32
+#define LPSS_SPI0_IRQ 36
+#define LPSS_SPI1_IRQ 37
+#define LPSS_SPI2_IRQ 18
+#define LPSS_SPI3_IRQ 23
+#define LPSS_UART0_IRQ 34
+#define LPSS_UART1_IRQ 35
+#define LPSS_UART2_IRQ 33
+
+#define HDA_IRQ 16
+#define SMBUS_IRQ 16
+#define TRACEHUB_IRQ 16
+
+#define PCIE_1_IRQ 16
+#define PCIE_2_IRQ 17
+#define PCIE_3_IRQ 18
+#define PCIE_4_IRQ 19
+#define PCIE_5_IRQ 16
+#define PCIE_6_IRQ 17
+#define PCIE_7_IRQ 18
+#define PCIE_8_IRQ 19
+#define PCIE_9_IRQ 16
+#define PCIE_10_IRQ 17
+#define PCIE_11_IRQ 18
+#define PCIE_12_IRQ 19
+
+#define SATA_IRQ 16
+
+#define xHCI_IRQ 16
+#define xDCI_IRQ 17
+#define CNVI_WIFI_IRQ 16
+
+#define CNVI_BT_IRQ 18
+
+#define THC0_IRQ 16
+#define THC1_IRQ 17
+
+#define ISH_IRQ 16
+
+#define TBT_PCIe0_IRQ 16
+#define TBT_PCIe1_IRQ 17
+#define TBT_PCIe2_IRQ 18
+#define TBT_PCIe3_IRQ 19
+
+#define HECI_1_IRQ 16
+#define HECI_2_IRQ 17
+#define HECI_3_IRQ 16
+#define HECI_4_IRQ 19
+
+#define PEG_IRQ 16
+#define IGFX_IRQ 16
+#define THERMAL_IRQ 16
+#define IPU_IRQ 16
+#define GNA_IRQ 16
+#endif /* _TGL_IRQ_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/itss.h b/src/soc/intel/jasperlake/include/soc/itss.h
new file mode 100644
index 0000000000..39794ead73
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/itss.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_TGL_ITSS_H
+#define SOC_INTEL_TGL_ITSS_H
+
+#define GPIO_IRQ_START 50
+#define GPIO_IRQ_END ITSS_MAX_IRQ
+
+#define ITSS_MAX_IRQ 119
+#define IRQS_PER_IPC 32
+#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
+
+#endif /* SOC_INTEL_TGL_ITSS_H */
diff --git a/src/soc/intel/jasperlake/include/soc/me.h b/src/soc/intel/jasperlake/include/soc/me.h
new file mode 100644
index 0000000000..94331b4c9e
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/me.h
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _TIGERLAKE_ME_H_
+#define _TIGERLAKE_ME_H_
+
+/* ME Host Firmware Status register 1 */
+union me_hfsts1 {
+ u32 data;
+ struct {
+ u32 working_state: 4;
+ u32 spi_protection_mode: 1;
+ u32 fpt_bad: 1;
+ u32 operation_state: 3;
+ u32 fw_init_complete: 1;
+ u32 ft_bup_ld_flr: 1;
+ u32 update_in_progress: 1;
+ u32 error_code: 4;
+ u32 operation_mode: 4;
+ u32 reset_count: 4;
+ u32 boot_options_present: 1;
+ u32 invoke_enhance_dbg_mode: 1;
+ u32 bist_test_state: 1;
+ u32 bist_reset_request: 1;
+ u32 current_power_source: 2;
+ u32 reserved: 1;
+ u32 d0i3_support_valid: 1;
+ } __packed fields;
+};
+
+/* ME Host Firmware Status Register 3 */
+union me_hfsts3 {
+ u32 data;
+ struct {
+ u32 reserved_0: 4;
+ u32 fw_sku: 3;
+ u32 reserved_7: 2;
+ u32 reserved_9: 2;
+ u32 resered_11: 3;
+ u32 resered_14: 16;
+ u32 reserved_30: 2;
+ } __packed fields;
+};
+#endif /* _TIGERLAKE_ME_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/meminit_jsl.h b/src/soc/intel/jasperlake/include/soc/meminit_jsl.h
new file mode 100644
index 0000000000..421e31d8e4
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/meminit_jsl.h
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_
+#define _SOC_JASPERLAKE_MEMCFG_INIT_H_
+
+#include <types.h>
+#include <fsp/soc_binding.h>
+
+/* Number of dq bits controlled per dqs */
+#define DQ_BITS_PER_DQS 8
+
+/* Number of memory packages, where a "package" represents a 64-bit solution */
+#define DDR_NUM_PACKAGES 2
+
+/* Number of DQ byte mappings */
+#define DDR_NUM_BYTE_MAPPINGS 6
+
+/* Number of memory DIMM slots available on Jasper Lake */
+#define NUM_DIMM_SLOT 4
+
+/* 64-bit Channel identification */
+enum {
+ DDR_CH0,
+ DDR_CH1,
+ DDR_NUM_CHANNELS
+};
+
+struct spd_by_pointer {
+ size_t spd_data_len;
+ uintptr_t spd_data_ptr;
+};
+
+enum mem_info_read_type {
+ READ_SPD_CBFS, /* Find SPD file in CBFS. */
+ READ_SMBUS, /* Read on-module SPD by SMBUS. */
+ READ_SPD_MEMPTR /* Find SPD data from pointer. */
+};
+
+struct spd_info {
+ enum mem_info_read_type read_type;
+ union spd_data_by {
+ /* To read on-module SPD when read_type is READ_SMBUS. */
+ uint8_t spd_smbus_address[NUM_DIMM_SLOT];
+
+ /* To identify SPD file when read_type is READ_SPD_CBFS. */
+ int spd_index;
+
+ /* To find SPD data when read_type is READ_SPD_MEMPTR. */
+ struct spd_by_pointer spd_data_ptr_info;
+ } spd_spec;
+};
+
+/* Board-specific memory dq mapping information */
+struct mb_cfg {
+
+ /*
+ * For each channel, there are 6 sets of DQ byte mappings,
+ * where each set has a package 0 and a package 1 value (package 0
+ * represents the first 64-bit lpddr4 chip combination, and package 1
+ * represents the second 64-bit lpddr4 chip combination).
+ * The first three sets are for CLK, CMD, and CTL.
+ * The fsp package actually expects 6 sets, even though the last 3 sets
+ * are not used in JSL.
+ * We let the meminit_dq_dqs_map routine take care of clearing the
+ * unused fields for the caller.
+ * Note that dq_map is only used by LPDDR; it does not need to be
+ * initialized for designs using DDR4.
+ */
+ uint8_t dq_map[DDR_NUM_CHANNELS][DDR_NUM_BYTE_MAPPINGS][DDR_NUM_PACKAGES];
+
+ /*
+ * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a
+ * mapping of a dq bit on the CPU to the bit it's connected to on
+ * the memory part. The array index represents the dqs bit number
+ * on the memory part, and the values in the array represent which
+ * pin on the CPU that DRAM pin connects to.
+ * dqs_map is only used by LPDDR; same comments apply as for dq_map
+ * above.
+ */
+ uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS];
+
+ /*
+ * Rcomp resistor values. These values represent the resistance in
+ * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+ * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+ */
+ uint16_t rcomp_resistor[3];
+
+ /*
+ * Rcomp target values. These will typically be the following
+ * values for Jasper Lake : { 80, 40, 40, 40, 30 }
+ */
+ uint16_t rcomp_targets[5];
+
+ /*
+ * Early Command Training Enable/Disable Control
+ * 1 = enable, 0 = disable
+ */
+ uint8_t ect;
+
+ /* Board type */
+ uint8_t UserBd;
+};
+
+/*
+ * Initialize default memory configurations for Jasper Lake.
+ */
+
+void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
+ const struct spd_info *spd_info, bool half_populated);
+
+#endif /* _SOC_JASPERLAKE_MEMCFG_INIT_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/meminit_tgl.h b/src/soc/intel/jasperlake/include/soc/meminit_tgl.h
new file mode 100644
index 0000000000..5573fb7110
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/meminit_tgl.h
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef _SOC_MEMINIT_TGL_H_
+#define _SOC_MEMINIT_TGL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fsp/soc_binding.h>
+
+#define BYTES_PER_CHANNEL 2
+#define BITS_PER_BYTE 8
+#define DQS_PER_CHANNEL 2
+#define NUM_CHANNELS 8
+
+struct spd_by_pointer {
+ size_t spd_data_len;
+ uintptr_t spd_data_ptr;
+};
+
+enum mem_info_read_type {
+ NOT_EXISTING, /* No memory in this channel */
+ READ_SPD_CBFS, /* Find spd file in CBFS. */
+ READ_SPD_MEMPTR /* Find spd data from pointer. */
+};
+
+struct spd_info {
+ enum mem_info_read_type read_type;
+ union spd_data_by {
+ /* To identify spd file when read_type is READ_SPD_CBFS. */
+ int spd_index;
+
+ /* To find spd data when read_type is READ_SPD_MEMPTR. */
+ struct spd_by_pointer spd_data_ptr_info;
+ } spd_spec;
+};
+
+/* Board-specific memory configuration information */
+struct mb_lpddr4x_cfg {
+ /* DQ mapping */
+ uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE];
+
+ /*
+ * DQS CPU<>DRAM map. Each array entry represents a
+ * mapping of a dq bit on the CPU to the bit it's connected to on
+ * the memory part. The array index represents the dqs bit number
+ * on the memory part, and the values in the array represent which
+ * pin on the CPU that DRAM pin connects to.
+ */
+ uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL];
+
+ /*
+ * Early Command Training Enable/Disable Control
+ * 1 = enable, 0 = disable
+ */
+ uint8_t ect;
+};
+
+/* Initialize default memory configurations for dimm0-only lpddr4x */
+void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg,
+ const struct mb_lpddr4x_cfg *board_cfg,
+ const struct spd_info *spd,
+ bool half_populated);
+
+#endif /* _SOC_MEMINIT_TGL_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/msr.h b/src/soc/intel/jasperlake/include/soc/msr.h
new file mode 100644
index 0000000000..7925ea76b0
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/msr.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_MSR_H_
+#define _SOC_MSR_H_
+
+#include <intelblocks/msr.h>
+
+#define MSR_PIC_MSG_CONTROL 0x2e
+#define MSR_VR_MISC_CONFIG2 0x636
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/nvs.h b/src/soc/intel/jasperlake/include/soc/nvs.h
new file mode 100644
index 0000000000..cfb189d381
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/nvs.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_NVS_H_
+#define _SOC_NVS_H_
+
+#include <intelblocks/nvs.h>
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/p2sb.h b/src/soc/intel/jasperlake/include/soc/p2sb.h
new file mode 100644
index 0000000000..d483ee399b
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/p2sb.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 3
+ */
+
+#ifndef _SOC_TIGERLAKE_P2SB_H_
+#define _SOC_TIGERLAKE_P2SB_H_
+
+#define HPTC_OFFSET 0x60
+#define HPTC_ADDR_ENABLE_BIT (1 << 7)
+
+#define PCH_P2SB_EPMASK0 0x220
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/pch.h b/src/soc/intel/jasperlake/include/soc/pch.h
new file mode 100644
index 0000000000..c2f497c1c8
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/pch.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_TIGERLAKE_PCH_H_
+#define _SOC_TIGERLAKE_PCH_H_
+
+#include <stdint.h>
+
+#define PCH_TGP 1
+#define PCH_JSP 2
+#define PCH_UNKNOWN_SERIES 0xFF
+
+#define PCIE_CLK_NOTUSED 0xFF
+#define PCIE_CLK_LAN 0x70
+#define PCIE_CLK_FREE 0x80
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h
new file mode 100644
index 0000000000..e729864817
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h
@@ -0,0 +1,209 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_TIGERLAKE_PCI_DEVS_H_
+#define _SOC_TIGERLAKE_PCI_DEVS_H_
+
+#include <device/pci_def.h>
+
+#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
+
+#if !defined(__SIMPLE_DEVICE__)
+#include <device/device.h>
+#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
+#else
+#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
+#endif
+
+/* System Agent Devices */
+
+#define SA_DEV_SLOT_ROOT 0x00
+#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
+#if defined(__SIMPLE_DEVICE__)
+#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
+#endif
+
+#define SA_DEV_SLOT_IGD 0x02
+#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
+#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
+
+#define SA_DEV_SLOT_DPTF 0x04
+#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0)
+#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0)
+
+#define SA_DEV_SLOT_TBT 0x07
+#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0)
+#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1)
+#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2)
+#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3)
+#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0)
+#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1)
+#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2)
+#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
+
+#define SA_DEV_SLOT_IPU 0x05
+#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
+#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
+
+/* PCH Devices */
+#define PCH_DEV_SLOT_SIO0 0x10
+#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2)
+#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6)
+#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7)
+#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2)
+#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6)
+#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7)
+
+#define PCH_DEV_SLOT_SIO1 0x11
+#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0)
+#define PCH_DEV_UART3 _PCH_DEV(SIO1, 0)
+
+#define PCH_DEV_SLOT_ISH 0x12
+#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0)
+#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6)
+#define PCH_DEV_ISH _PCH_DEV(ISH, 0)
+#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6)
+
+#define PCH_DEV_SLOT_SIO2 0x13
+#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0)
+#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0)
+
+#define PCH_DEV_SLOT_XHCI 0x14
+#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
+#define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1)
+#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2)
+#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3)
+#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
+#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1)
+#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2)
+#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3)
+
+#if CONFIG(SOC_INTEL_JASPERLAKE_COPY)
+#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5)
+#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5)
+#endif
+
+#define PCH_DEV_SLOT_SIO3 0x15
+#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0)
+#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1)
+#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2)
+#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3)
+#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0)
+#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1)
+#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2)
+#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3)
+
+#define PCH_DEV_SLOT_CSE 0x16
+#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)
+#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)
+#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2)
+#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3)
+#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)
+#define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5)
+#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
+#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)
+#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2)
+#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3)
+#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
+#define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5)
+
+#define PCH_DEV_SLOT_SATA 0x17
+#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0)
+#define PCH_DEV_SATA _PCH_DEV(SATA, 0)
+
+#define PCH_DEV_SLOT_SIO4 0x19
+#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0)
+#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1)
+#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2)
+#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0)
+#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1)
+#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2)
+
+#if CONFIG(SOC_INTEL_JASPERLAKE_COPY)
+#define PCH_DEV_SLOT_STORAGE 0x1a
+#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0)
+#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0)
+#endif
+
+#define PCH_DEV_SLOT_PCIE 0x1c
+#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0)
+#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1)
+#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE, 2)
+#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3)
+#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4)
+#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5)
+#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6)
+#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7)
+#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0)
+#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1)
+#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2)
+#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3)
+#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4)
+#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5)
+#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6)
+#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7)
+
+#define PCH_DEV_SLOT_PCIE_1 0x1d
+#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0)
+#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)
+#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)
+#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)
+#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0)
+#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1)
+#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2)
+#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3)
+
+#define PCH_DEV_SLOT_SIO5 0x1e
+#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0)
+#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1)
+#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2)
+#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3)
+#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0)
+#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1)
+#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2)
+#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3)
+
+#define PCH_DEV_SLOT_ESPI 0x1f
+#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI
+#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0)
+#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1)
+#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2)
+#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3)
+#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4)
+#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5)
+#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6)
+#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7)
+#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0)
+#define PCH_DEV_LPC PCH_DEV_ESPI
+#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1)
+
+#if !ENV_RAMSTAGE
+/*
+ * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets
+ * hidden from PCI bus after call to FSP-S. This leads to resource allocator
+ * dropping it from the root bus as unused device. All references to PCH_DEV_PMC
+ * would then return NULL and can go unnoticed if not handled properly. Since,
+ * this device does not have any special chip config associated with it, it is
+ * okay to not provide the definition for it in ramstage.
+ */
+#define PCH_DEV_PMC _PCH_DEV(ESPI, 2)
+#endif
+
+#define PCH_DEV_HDA _PCH_DEV(ESPI, 3)
+#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4)
+#define PCH_DEV_SPI _PCH_DEV(ESPI, 5)
+#define PCH_DEV_GBE _PCH_DEV(ESPI, 6)
+#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7)
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/pcr_ids.h b/src/soc/intel/jasperlake/include/soc/pcr_ids.h
new file mode 100644
index 0000000000..4143892f87
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/pcr_ids.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 31-35
+ */
+
+#ifndef SOC_TIGERLAKE_PCR_H
+#define SOC_TIGERLAKE_PCR_H
+/*
+ * Port ids
+ */
+#define PID_EMMC 0x52
+#define PID_SDX 0x53
+
+#define PID_GPIOCOM0 0x6e
+#define PID_GPIOCOM1 0x6d
+#define PID_GPIOCOM2 0x6c
+#define PID_GPIOCOM4 0x6a
+#define PID_GPIOCOM5 0x69
+
+#define PID_DMI 0x88
+#define PID_PSTH 0x89
+#define PID_CSME0 0x90
+#define PID_ISCLK 0xad
+#define PID_PSF1 0xba
+#define PID_PSF2 0xbb
+#define PID_PSF3 0xbc
+#define PID_PSF4 0xbd
+#define PID_SCS 0xc0
+#define PID_RTC 0xc3
+#define PID_ITSS 0xc4
+#define PID_ESPI 0xc7
+#define PID_SERIALIO 0xcb
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h
new file mode 100644
index 0000000000..14fa5d0c08
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/pm.h
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 4
+ */
+
+#ifndef _SOC_PM_H_
+#define _SOC_PM_H_
+
+#define PM1_STS 0x00
+#define WAK_STS (1 << 15)
+#define PCIEXPWAK_STS (1 << 14)
+#define PRBTNOR_STS (1 << 11)
+#define RTC_STS (1 << 10)
+#define PWRBTN_STS (1 << 8)
+#define GBL_STS (1 << 5)
+#define BM_STS (1 << 4)
+#define TMROF_STS (1 << 0)
+#define PM1_EN 0x02
+#define PCIEXPWAK_DIS (1 << 14)
+#define RTC_EN (1 << 10)
+#define PWRBTN_EN (1 << 8)
+#define GBL_EN (1 << 5)
+#define TMROF_EN (1 << 0)
+#define PM1_CNT 0x04
+#define GBL_RLS (1 << 2)
+#define BM_RLD (1 << 1)
+#define SCI_EN (1 << 0)
+#define PM1_TMR 0x08
+#define SMI_EN 0x30
+#define XHCI_SMI_EN (1 << 31)
+#define ME_SMI_EN (1 << 30)
+#define ESPI_SMI_EN (1 << 28)
+#define GPIO_UNLOCK_SMI_EN (1 << 27)
+#define INTEL_USB2_EN (1 << 18)
+#define LEGACY_USB2_EN (1 << 17)
+#define PERIODIC_EN (1 << 14)
+#define TCO_SMI_EN (1 << 13)
+#define MCSMI_EN (1 << 11)
+#define BIOS_RLS (1 << 7)
+#define SWSMI_TMR_EN (1 << 6)
+#define APMC_EN (1 << 5)
+#define SLP_SMI_EN (1 << 4)
+#define LEGACY_USB_EN (1 << 3)
+#define BIOS_EN (1 << 2)
+#define EOS (1 << 1)
+#define GBL_SMI_EN (1 << 0)
+#define SMI_STS 0x34
+#define SMI_STS_BITS 32
+#define XHCI_SMI_STS_BIT 31
+#define ME_SMI_STS_BIT 30
+#define ESPI_SMI_STS_BIT 28
+#define GPIO_UNLOCK_SMI_STS_BIT 27
+#define SPI_SMI_STS_BIT 26
+#define SCC_SMI_STS_BIT 25
+#define MONITOR_STS_BIT 21
+#define PCI_EXP_SMI_STS_BIT 20
+#define SMBUS_SMI_STS_BIT 16
+#define SERIRQ_SMI_STS_BIT 15
+#define PERIODIC_STS_BIT 14
+#define TCO_STS_BIT 13
+#define DEVMON_STS_BIT 12
+#define MCSMI_STS_BIT 11
+#define GPIO_STS_BIT 10
+#define GPE0_STS_BIT 9
+#define PM1_STS_BIT 8
+#define SWSMI_TMR_STS_BIT 6
+#define APM_STS_BIT 5
+#define SMI_ON_SLP_EN_STS_BIT 4
+#define LEGACY_USB_STS_BIT 3
+#define BIOS_STS_BIT 2
+#define GPE_CNTL 0x42
+#define SWGPE_CTRL (1 << 1)
+#define DEVACT_STS 0x44
+#define PM2_CNT 0x50
+
+#define GPE0_REG_MAX 4
+#define GPE0_REG_SIZE 32
+#define GPE0_STS(x) (0x60 + ((x) * 4))
+#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */
+#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */
+#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */
+#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */
+#define GPE_STS_RSVD GPE_STD
+#define WADT_STS (1 << 18)
+#define GPIO_T2_STS (1 << 15)
+#define ESPI_STS (1 << 14)
+#define PME_B0_STS (1 << 13)
+#define ME_SCI_STS (1 << 12)
+#define PME_STS (1 << 11)
+#define BATLOW_STS (1 << 10)
+#define PCI_EXP_STS (1 << 9)
+#define SMB_WAK_STS (1 << 7)
+#define TCOSCI_STS (1 << 6)
+#define SWGPE_STS (1 << 2)
+#define HOT_PLUG_STS (1 << 1)
+#define GPE0_EN(x) (0x70 + ((x) * 4))
+#define WADT_EN (1 << 18)
+#define GPIO_T2_EN (1 << 15)
+#define ESPI_EN (1 << 14)
+#define PME_B0_EN_BIT 13
+#define PME_B0_EN (1 << PME_B0_EN_BIT)
+#define ME_SCI_EN (1 << 12)
+#define PME_EN (1 << 11)
+#define BATLOW_EN (1 << 10)
+#define PCI_EXP_EN (1 << 9)
+#define TCOSCI_EN (1 << 6)
+#define SWGPE_EN (1 << 2)
+#define HOT_PLUG_EN (1 << 1)
+
+#define EN_BLOCK 3
+
+/*
+ * Enable SMI generation:
+ * - on APMC writes (io 0xb2)
+ * - on writes to SLP_EN (sleep states)
+ * - on writes to GBL_RLS (bios commands)
+ * - on eSPI events (does nothing on LPC systems)
+ * No SMIs:
+ * - on TCO events, unless enabled in common code
+ * - on microcontroller writes (io 0x62/0x66)
+ */
+#define ENABLE_SMI_PARAMS \
+ (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
+
+#define PSS_RATIO_STEP 2
+#define PSS_MAX_ENTRIES 8
+#define PSS_LATENCY_TRANSITION 10
+#define PSS_LATENCY_BUSMASTER 10
+
+#if !defined(__ACPI__)
+
+#include <arch/acpi.h>
+#include <soc/gpe.h>
+#include <soc/iomap.h>
+#include <soc/smbus.h>
+#include <soc/pmc.h>
+
+struct chipset_power_state {
+ uint16_t pm1_sts;
+ uint16_t pm1_en;
+ uint32_t pm1_cnt;
+ uint16_t tco1_sts;
+ uint16_t tco2_sts;
+ uint32_t gpe0_sts[4];
+ uint32_t gpe0_en[4];
+ uint32_t gen_pmcon_a;
+ uint32_t gen_pmcon_b;
+ uint32_t gblrst_cause[2];
+ uint32_t prev_sleep_state;
+} __packed;
+
+/* Get base address PMC memory mapped registers. */
+uint8_t *pmc_mmio_regs(void);
+
+/* Get base address of TCO I/O registers. */
+uint16_t smbus_tco_regs(void);
+
+/* Set the DISB after DRAM init */
+void pmc_set_disb(void);
+
+/* Clear PMCON status bits */
+void pmc_clear_pmcon_sts(void);
+
+/* STM Support */
+uint16_t get_pmbase(void);
+#endif /* !defined(__ACPI__) */
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h
new file mode 100644
index 0000000000..0ec1d36e44
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/pmc.h
@@ -0,0 +1,168 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_TIGERLAKE_PMC_H_
+#define _SOC_TIGERLAKE_PMC_H_
+
+/* PCI Configuration Space (D31:F2): PMC */
+#define PWRMBASE 0x10
+#define ABASE 0x20
+
+/* Memory mapped IO registers in PMC */
+#define GEN_PMCON_A 0x1020
+#define DC_PP_DIS (1 << 30)
+#define DSX_PP_DIS (1 << 29)
+#define AG3_PP_EN (1 << 28)
+#define SX_PP_EN (1 << 27)
+#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26)
+#define GBL_RST_STS (1 << 24)
+#define DISB (1 << 23)
+#define ALLOW_OPI_PLL_SD_INC0 (1 << 22)
+#define MEM_SR (1 << 21)
+#define ALLOW_SPXB_CG_INC0 (1 << 20)
+#define ALLOW_L1LOW_C0 (1 << 19)
+#define MS4V (1 << 18)
+#define ALLOW_L1LOW_OPI_ON (1 << 17)
+#define SUS_PWR_FLR (1 << 16)
+#define PME_B0_S5_DIS (1 << 15)
+#define PWR_FLR (1 << 14)
+#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13)
+#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
+#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10)
+#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)
+#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10)
+#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10)
+#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10)
+#define HOST_RST_STS (1 << 9)
+#define ESPI_SMI_LOCK (1 << 8)
+#define S4MAW_MASK (3 << 4)
+#define S4MAW_1S (1 << 4)
+#define S4MAW_2S (2 << 4)
+#define S4MAW_3S (3 << 4)
+#define S4MAW_4S (0 << 4)
+#define S4ASE (1 << 3)
+#define PER_SMI_SEL_MASK (3 << 1)
+#define SMI_RATE_64S (0 << 1)
+#define SMI_RATE_32S (1 << 1)
+#define SMI_RATE_16S (2 << 1)
+#define SMI_RATE_8S (3 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+
+#define GEN_PMCON_B 0x1024
+#define SLP_STR_POL_LOCK (1 << 18)
+#define ACPI_BASE_LOCK (1 << 17)
+#define PM_DATA_BAR_DIS (1 << 16)
+#define WOL_EN_OVRD (1 << 13)
+#define BIOS_PCI_EXP_EN (1 << 10)
+#define PWRBTN_LVL (1 << 9)
+#define SMI_LOCK (1 << 4)
+#define RTC_BATTERY_DEAD (1 << 2)
+
+#define ETR 0x1048
+#define CF9_LOCK (1 << 31)
+#define CF9_GLB_RST (1 << 20)
+
+#define SSML 0x104C
+#define SSML_SSL_DS (0 << 0)
+#define SSML_SSL_EN (1 << 0)
+
+#define SSMC 0x1050
+#define SSMC_SSMS (1 << 0)
+
+#define SSMD 0x1054
+#define SSMD_SSD_MASK (0xffff << 0)
+
+#define PRSTS 0x1810
+
+#define S3_PWRGATE_POL 0x1828
+#define S3DC_GATE_SUS (1 << 1)
+#define S3AC_GATE_SUS (1 << 0)
+
+#define S4_PWRGATE_POL 0x182c
+#define S4DC_GATE_SUS (1 << 1)
+#define S4AC_GATE_SUS (1 << 0)
+
+#define S5_PWRGATE_POL 0x1830
+#define S5DC_GATE_SUS (1 << 15)
+#define S5AC_GATE_SUS (1 << 14)
+
+#define DSX_CFG 0x1834
+#define REQ_CNV_NOWAKE_DSX (1 << 4)
+#define REQ_BATLOW_DSX (1 << 3)
+#define DSX_EN_WAKE_PIN (1 << 2)
+#define DSX_DIS_AC_PRESENT_PD (1 << 1)
+#define DSX_EN_LAN_WAKE_PIN (1 << 0)
+#define DSX_CFG_MASK (0x1f << 0)
+
+#define PMSYNC_TPR_CFG 0x18C4
+#define PCH2CPU_TPR_CFG_LOCK (1 << 31)
+#define PCH2CPU_TT_EN (1 << 26)
+
+#define PCH_PWRM_ACPI_TMR_CTL 0x18FC
+#define GPIO_GPE_CFG 0x1920
+#define GPE0_DWX_MASK 0xf
+#define GPE0_DW_SHIFT(x) (4*(x))
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
+
+ #define PMC_GPP_B 0x0
+ #define PMC_GPP_T 0x1
+ #define PMC_GPP_A 0x2
+ #define PMC_GPP_R 0x3
+ #define PMC_GPD 0x4
+ #define PMC_GPP_S 0x5
+ #define PMC_GPP_H 0x6
+ #define PMC_GPP_D 0x7
+ #define PMC_GPP_U 0x8
+ #define PMC_GPP_F 0xA
+ #define PMC_GPP_C 0xB
+ #define PMC_GPP_E 0xC
+
+#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY)
+
+ #define PMC_GPP_A 0x0
+ #define PMC_GPP_B 0x1
+ #define PMC_GPP_F 0x2
+ #define PMC_GPD 0x3
+ #define PMC_GPP_R 0x4
+ #define PMC_GPP_S 0x6
+ #define PMC_GPP_D 0x7
+ #define PMC_GPP_C 0x8
+ #define PMC_GPP_H 0xA
+ #define PMC_GPP_E 0xF
+
+#endif
+
+#define GBLRST_CAUSE0 0x1924
+#define GBLRST_CAUSE0_THERMTRIP (1 << 5)
+#define GBLRST_CAUSE1 0x1928
+
+#define CPPMVRIC 0x1B1C
+#define XTALSDQDIS (1 << 22)
+
+#define IRQ_REG ACTL
+#define SCI_IRQ_ADJUST 0
+#define ACTL 0x1BD8
+#define PWRM_EN (1 << 8)
+#define ACPI_EN (1 << 7)
+#define SCI_IRQ_SEL (7 << 0)
+
+#define SCIS_IRQ9 0
+#define SCIS_IRQ10 1
+#define SCIS_IRQ11 2
+#define SCIS_IRQ20 4
+#define SCIS_IRQ21 5
+#define SCIS_IRQ22 6
+#define SCIS_IRQ23 7
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/ramstage.h b/src/soc/intel/jasperlake/include/soc/ramstage.h
new file mode 100644
index 0000000000..a8c8fdd7b2
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/ramstage.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <device/device.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <soc/soc_chip.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void soc_init_pre_device(void *chip_info);
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/romstage.h b/src/soc/intel/jasperlake/include/soc/romstage.h
new file mode 100644
index 0000000000..1672e8b5ca
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/romstage.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <fsp/api.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd);
+void systemagent_early_init(void);
+void pch_init(void);
+
+/* Board type */
+enum board_type {
+ BOARD_TYPE_MOBILE = 0,
+ BOARD_TYPE_DESKTOP = 1,
+ BOARD_TYPE_ULT_ULX = 5,
+ BOARD_TYPE_SERVER = 7
+};
+
+#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/serialio.h b/src/soc/intel/jasperlake/include/soc/serialio.h
new file mode 100644
index 0000000000..509f0b0f14
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/serialio.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SERIALIO_H_
+#define _SERIALIO_H_
+
+enum {
+ PchSerialIoDisabled,
+ PchSerialIoPci,
+ PchSerialIoHidden,
+ PchSerialIoLegacyUart,
+ PchSerialIoSkipInit
+};
+
+enum {
+ PchSerialIoIndexI2C0,
+ PchSerialIoIndexI2C1,
+ PchSerialIoIndexI2C2,
+ PchSerialIoIndexI2C3,
+ PchSerialIoIndexI2C4,
+ PchSerialIoIndexI2C5,
+};
+
+enum {
+ PchSerialIoIndexGSPI0,
+ PchSerialIoIndexGSPI1,
+ PchSerialIoIndexGSPI2,
+ PchSerialIoIndexGSPI3,
+};
+
+enum {
+ PchSerialIoIndexUART0,
+ PchSerialIoIndexUART1,
+ PchSerialIoIndexUART2,
+};
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/smbus.h b/src/soc/intel/jasperlake/include/soc/smbus.h
new file mode 100644
index 0000000000..3fb8291698
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/smbus.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 6
+ */
+
+#ifndef _SOC_TIGERLAKE_SMBUS_H_
+#define _SOC_TIGERLAKE_SMBUS_H_
+
+/* IO and MMIO registers under primary BAR */
+
+/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
+#define TCO1_STS 0x04
+#define TCO_TIMEOUT (1 << 3)
+#define TCO2_STS 0x06
+#define TCO_STS_SECOND_TO (1 << 1)
+#define TCO_INTRD_DET (1 << 0)
+#define TCO1_CNT 0x08
+#define TCO_LOCK (1 << 12)
+#define TCO_TMR_HLT (1 << 11)
+#define TCO2_CNT 0x0A
+#define TCO_INTRD_SEL_MASK (3 << 1)
+#define TCO_INTRD_SEL_SMI (1 << 2)
+#define TCO_INTRD_SEL_INT (1 << 1)
+
+/*
+ * Default slave address value for PCH. This value is set to match default
+ * value set by hardware. It is useful since PCH is able to respond even
+ * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
+ */
+#define SMBUS_SLAVE_ADDR 0x44
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/soc_chip.h b/src/soc/intel/jasperlake/include/soc/soc_chip.h
new file mode 100644
index 0000000000..250aa9a0aa
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/soc_chip.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_TIGERLAKE_SOC_CHIP_H_
+#define _SOC_TIGERLAKE_SOC_CHIP_H_
+
+#include "../../chip.h"
+
+#endif /* _SOC_TIGERLAKE_SOC_CHIP_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h
new file mode 100644
index 0000000000..d8c8ad47da
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/systemagent.h
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor SA Datasheet
+ * Document number: 571131
+ * Chapter number: 3
+ */
+
+#ifndef SOC_TIGERLAKE_SYSTEMAGENT_H
+#define SOC_TIGERLAKE_SYSTEMAGENT_H
+
+#include <intelblocks/systemagent.h>
+
+/* Device 0:0.0 PCI configuration space */
+
+#define EPBAR 0x40
+#define DMIBAR 0x68
+#define SMRAM 0x88 /* System Management RAM Control */
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRAME (1 << 3)
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+#define CAPID0_A 0xe4
+#define VTD_DISABLE (1 << 23)
+
+#define BIOS_RESET_CPL 0x5da8
+#define GFXVTBAR 0x5400
+#define EDRAMBAR 0x5408
+#define VTVC0BAR 0x5410
+#define REGBAR 0x5420
+#define IPUVTBAR 0x7880
+#define TBT0BAR 0x7888
+#define TBT1BAR 0x7890
+#define TBT2BAR 0x7898
+#define TBT3BAR 0x78A0
+#define MAX_TBT_PCIE_PORT 4
+
+#define VTBAR_ENABLED 0x01
+#define VTBAR_MASK 0x7ffffff000ull
+
+#define MCH_PKG_POWER_LIMIT_LO 0x59a0
+#define MCH_PKG_POWER_LIMIT_HI 0x59a4
+#define MCH_DDR_POWER_LIMIT_LO 0x58e0
+#define MCH_DDR_POWER_LIMIT_HI 0x58e4
+
+#define IMRBASE 0x6A40
+#define IMRLIMIT 0x6A48
+
+static const struct sa_mmio_descriptor soc_vtd_resources[] = {
+ { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
+ { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" },
+ { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" },
+ { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" },
+ { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" },
+ { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" },
+ { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
+};
+
+#define V_P2SB_CFG_IBDF_BUS 0
+#define V_P2SB_CFG_IBDF_DEV 30
+#define V_P2SB_CFG_IBDF_FUNC 7
+#define V_P2SB_CFG_HBDF_BUS 0
+#define V_P2SB_CFG_HBDF_DEV 30
+#define V_P2SB_CFG_HBDF_FUNC 6
+
+#endif
diff --git a/src/soc/intel/jasperlake/include/soc/usb.h b/src/soc/intel/jasperlake/include/soc/usb.h
new file mode 100644
index 0000000000..33c0bf0bf9
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/usb.h
@@ -0,0 +1,151 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef _SOC_USB_H_
+#define _SOC_USB_H_
+
+#include <stdint.h>
+
+/* Per Port HS Transmitter Emphasis */
+#define USB2_EMP_OFF 0
+#define USB2_DE_EMP_ON 1
+#define USB2_PRE_EMP_ON 2
+#define USB2_DE_EMP_ON_PRE_EMP_ON 3
+
+/* Per Port Half Bit Pre-emphasis */
+#define USB2_FULL_BIT_PRE_EMP 0
+#define USB2_HALF_BIT_PRE_EMP 1
+
+/* Per Port HS Preemphasis Bias */
+#define USB2_BIAS_0MV 0
+#define USB2_BIAS_11P25MV 1
+#define USB2_BIAS_16P9MV 2
+#define USB2_BIAS_28P15MV 3
+#define USB2_BIAS_39P35MV 5
+#define USB2_BIAS_45MV 6
+#define USB2_BIAS_56P3MV 7
+
+struct usb2_port_config {
+ uint8_t enable;
+ uint8_t ocpin;
+ uint8_t tx_bias;
+ uint8_t tx_emp_enable;
+ uint8_t pre_emp_bias;
+ uint8_t pre_emp_bit;
+};
+
+/* USB Overcurrent pins definition */
+enum {
+ OC0 = 0,
+ OC1,
+ OC2,
+ OC3,
+ OC4,
+ OC5,
+ OC6,
+ OC7,
+ OCMAX,
+ OC_SKIP = 0xff, /* Skip OC programming */
+};
+
+/* Standard USB Port based on length:
+ * - External
+ * - Back Panel
+ * - OTG
+ * - M.2
+ * - Internal device down */
+
+#define USB2_PORT_EMPTY { \
+ .enable = 0, \
+ .ocpin = OC_SKIP, \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_EMP_OFF, \
+ .pre_emp_bias = USB2_BIAS_0MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length = 11.5"-12" */
+#define USB2_PORT_LONG(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_bias = USB2_BIAS_39P35MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56P3MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length = 6"-11.49" */
+#define USB2_PORT_MID(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56P3MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length = 3"-5.99" */
+#define USB2_PORT_SHORT(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_bias = USB2_BIAS_39P35MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_39P35MV, \
+ .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
+}
+
+/* Max TX and Pre-emp settings */
+#define USB2_PORT_MAX(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_bias = USB2_BIAS_56P3MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56P3MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Type-C Port, no BC1.2 charge detect module / MUX
+ * Length = 3.0" - 9.00" */
+#define USB2_PORT_TYPE_C(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56P3MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+struct usb3_port_config {
+ uint8_t enable;
+ uint8_t ocpin;
+ uint8_t tx_de_emp;
+ uint8_t tx_downscale_amp;
+};
+
+#define USB3_PORT_EMPTY { \
+ .enable = 0, \
+ .ocpin = OC_SKIP, \
+ .tx_de_emp = 0x00, \
+ .tx_downscale_amp = 0x00, \
+}
+
+#define USB3_PORT_DEFAULT(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_de_emp = 0x0, \
+ .tx_downscale_amp = 0x00, \
+}
+
+#endif
diff --git a/src/soc/intel/jasperlake/lockdown.c b/src/soc/intel/jasperlake/lockdown.c
new file mode 100644
index 0000000000..18d4fa728e
--- /dev/null
+++ b/src/soc/intel/jasperlake/lockdown.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 4
+ */
+
+#include <device/mmio.h>
+#include <intelblocks/cfg.h>
+#include <intelpch/lockdown.h>
+#include <soc/pm.h>
+
+static void pmc_lock_pmsync(void)
+{
+ uint8_t *pmcbase;
+ uint32_t pmsyncreg;
+
+ pmcbase = pmc_mmio_regs();
+
+ pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
+ pmsyncreg |= PCH2CPU_TPR_CFG_LOCK;
+ write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
+}
+
+static void pmc_lock_abase(void)
+{
+ uint8_t *pmcbase;
+ uint32_t reg32;
+
+ pmcbase = pmc_mmio_regs();
+
+ reg32 = read32(pmcbase + GEN_PMCON_B);
+ reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
+ write32(pmcbase + GEN_PMCON_B, reg32);
+}
+
+static void pmc_lock_smi(void)
+{
+ uint8_t *pmcbase;
+ uint8_t reg8;
+
+ pmcbase = pmc_mmio_regs();
+
+ reg8 = read8(pmcbase + GEN_PMCON_B);
+ reg8 |= SMI_LOCK;
+ write8(pmcbase + GEN_PMCON_B, reg8);
+}
+
+static void pmc_lockdown_cfg(int chipset_lockdown)
+{
+ /* PMSYNC */
+ pmc_lock_pmsync();
+ /* Lock down ABASE and sleep stretching policy */
+ pmc_lock_abase();
+
+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
+ pmc_lock_smi();
+}
+
+void soc_lockdown_config(int chipset_lockdown)
+{
+ /* PMC lock down configuration */
+ pmc_lockdown_cfg(chipset_lockdown);
+}
diff --git a/src/soc/intel/jasperlake/meminit_jsl.c b/src/soc/intel/jasperlake/meminit_jsl.c
new file mode 100644
index 0000000000..c68d2100fc
--- /dev/null
+++ b/src/soc/intel/jasperlake/meminit_jsl.c
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/meminit_jsl.h>
+#include <spd_bin.h>
+#include <string.h>
+
+static void spd_read_from_cbfs(const struct spd_info *spd_info, uintptr_t *spd_data_ptr,
+ size_t *spd_data_len)
+{
+ struct region_device spd_rdev;
+ size_t spd_index = spd_info->spd_spec.spd_index;
+
+ printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index);
+ if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
+ die("spd.bin not found or incorrect index\n");
+
+ *spd_data_len = region_device_sz(&spd_rdev);
+
+ /* Memory leak is ok since we have memory mapped boot media */
+ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
+
+ *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);
+}
+
+static void get_spd_data(const struct spd_info *spd_info, uintptr_t *spd_data_ptr,
+ size_t *spd_data_len)
+{
+ if (spd_info->read_type == READ_SPD_MEMPTR) {
+ *spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr;
+ *spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len;
+ return;
+ }
+
+ if (spd_info->read_type == READ_SPD_CBFS) {
+ spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len);
+ return;
+ }
+
+ die("no valid way to read SPD info");
+}
+
+static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
+ bool half_populated)
+{
+ memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor,
+ sizeof(mem_cfg->RcompResistor));
+
+ memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets,
+ sizeof(mem_cfg->RcompTarget));
+
+ memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0],
+ sizeof(board_cfg->dq_map[DDR_CH0]));
+
+ memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0],
+ sizeof(board_cfg->dqs_map[DDR_CH0]));
+
+ if (half_populated)
+ return;
+
+ memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1],
+ sizeof(board_cfg->dq_map[DDR_CH1]));
+
+ memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1],
+ sizeof(board_cfg->dqs_map[DDR_CH1]));
+}
+
+static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
+ uintptr_t spd_data_ptr, bool half_populated)
+{
+ /* Channel 0 */
+ mem_cfg->MemorySpdPtr00 = spd_data_ptr;
+ mem_cfg->MemorySpdPtr01 = 0;
+
+ if (half_populated) {
+ printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__);
+ spd_data_ptr = 0;
+ }
+
+ /* Channel 1 */
+ mem_cfg->MemorySpdPtr10 = spd_data_ptr;
+ mem_cfg->MemorySpdPtr11 = 0;
+
+ meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated);
+}
+
+/* Initialize onboard memory configurations for lpddr4x */
+void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
+ const struct spd_info *spd_info, bool half_populated)
+{
+
+ if (spd_info->read_type == READ_SMBUS) {
+ for (int i = 0; i < NUM_DIMM_SLOT; i++)
+ mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i];
+
+ meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated);
+ } else {
+ uintptr_t spd_data_ptr = 0;
+ size_t spd_data_len = 0;
+ memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable));
+ get_spd_data(spd_info, &spd_data_ptr, &spd_data_len);
+ print_spd_info((unsigned char *)spd_data_ptr);
+
+ mem_cfg->MemorySpdDataLen = spd_data_len;
+ meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated);
+ }
+
+ /* Early Command Training Enabled */
+ mem_cfg->ECT = board_cfg->ect;
+
+ mem_cfg->UserBd = board_cfg->UserBd;
+}
diff --git a/src/soc/intel/jasperlake/meminit_tgl.c b/src/soc/intel/jasperlake/meminit_tgl.c
new file mode 100644
index 0000000000..a0e5107998
--- /dev/null
+++ b/src/soc/intel/jasperlake/meminit_tgl.c
@@ -0,0 +1,163 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <assert.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/meminit_tgl.h>
+#include <spd_bin.h>
+#include <string.h>
+
+enum dimm_enable_options {
+ ENABLE_BOTH_DIMMS = 0,
+ DISABLE_DIMM0 = 1,
+ DISABLE_DIMM1 = 2,
+ DISABLE_BOTH_DIMMS = 3
+};
+
+#define MEM_INIT_CH_DQ_DQS_MAP(_mem_cfg, _b_cfg, _ch) \
+ do { \
+ memcpy(&_mem_cfg->DqMapCpu2DramCh ## _ch, \
+ &_b_cfg->dq_map[_ch], \
+ sizeof(_b_cfg->dq_map[_ch])); \
+ memcpy(&_mem_cfg->DqsMapCpu2DramCh ## _ch, \
+ &_b_cfg->dqs_map[_ch], \
+ sizeof(_b_cfg->dqs_map[_ch])); \
+ } while (0)
+
+
+static void spd_read_from_cbfs(const struct spd_info *spd,
+ uintptr_t *spd_data_ptr, size_t *spd_data_len)
+{
+ struct region_device spd_rdev;
+ size_t spd_index = spd->spd_spec.spd_index;
+
+ printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index);
+ if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
+ die("spd.bin not found or incorrect index\n");
+
+ *spd_data_len = region_device_sz(&spd_rdev);
+
+ /* Memory leak is ok since we have memory mapped boot media */
+ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
+
+ *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);
+}
+
+static void get_spd_data(const struct spd_info *spd,
+ uintptr_t *spd_data_ptr, size_t *spd_data_len)
+{
+ if (spd->read_type == READ_SPD_MEMPTR) {
+ *spd_data_ptr = spd->spd_spec.spd_data_ptr_info.spd_data_ptr;
+ *spd_data_len = spd->spd_spec.spd_data_ptr_info.spd_data_len;
+ return;
+ }
+
+ if (spd->read_type == READ_SPD_CBFS) {
+ spd_read_from_cbfs(spd, spd_data_ptr, spd_data_len);
+ return;
+ }
+
+ die("no valid way to read SPD info");
+}
+
+static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg,
+ const struct mb_lpddr4x_cfg *board_cfg,
+ bool half_populated)
+{
+ MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 0);
+ MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 1);
+ MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 2);
+ MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 3);
+
+ if (half_populated)
+ return;
+
+ MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 4);
+ MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 5);
+ MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 6);
+ MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 7);
+}
+
+static void meminit_channels_dimm0(FSP_M_CONFIG *mem_cfg,
+ const struct mb_lpddr4x_cfg *board_cfg,
+ uintptr_t spd_data_ptr,
+ bool half_populated)
+{
+ uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */
+
+ /* Channel 0 */
+ mem_cfg->Reserved9[0] = dimm_cfg;
+ mem_cfg->MemorySpdPtr00 = spd_data_ptr;
+ mem_cfg->MemorySpdPtr01 = 0;
+
+ /* Channel 1 */
+ mem_cfg->Reserved9[1] = dimm_cfg;
+ mem_cfg->MemorySpdPtr02 = spd_data_ptr;
+ mem_cfg->MemorySpdPtr03 = 0;
+
+ /* Channel 2 */
+ mem_cfg->Reserved9[2] = dimm_cfg;
+ mem_cfg->MemorySpdPtr04 = spd_data_ptr;
+ mem_cfg->MemorySpdPtr05 = 0;
+
+ /* Channel 3 */
+ mem_cfg->Reserved9[3] = dimm_cfg;
+ mem_cfg->MemorySpdPtr06 = spd_data_ptr;
+ mem_cfg->MemorySpdPtr07 = 0;
+
+ if (half_populated) {
+ printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__);
+ dimm_cfg = DISABLE_BOTH_DIMMS;
+ spd_data_ptr = 0;
+ }
+
+ /* Channel 4 */
+ mem_cfg->Reserved9[4] = dimm_cfg;
+ mem_cfg->MemorySpdPtr08 = spd_data_ptr;
+ mem_cfg->MemorySpdPtr09 = 0;
+
+ /* Channel 5 */
+ mem_cfg->Reserved9[5] = dimm_cfg;
+ mem_cfg->MemorySpdPtr10 = spd_data_ptr;
+ mem_cfg->MemorySpdPtr11 = 0;
+
+ /* Channel 6 */
+ mem_cfg->Reserved9[6] = dimm_cfg;
+ mem_cfg->MemorySpdPtr12 = spd_data_ptr;
+ mem_cfg->MemorySpdPtr13 = 0;
+
+ /* Channel 7 */
+ mem_cfg->Reserved9[7] = dimm_cfg;
+ mem_cfg->MemorySpdPtr14 = spd_data_ptr;
+ mem_cfg->MemorySpdPtr15 = 0;
+
+ meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated);
+}
+
+/* Initialize onboard memory configurations for lpddr4x */
+void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg,
+ const struct mb_lpddr4x_cfg *board_cfg,
+ const struct spd_info *spd,
+ bool half_populated)
+
+{
+ size_t spd_data_len;
+ uintptr_t spd_data_ptr;
+
+ get_spd_data(spd, &spd_data_ptr, &spd_data_len);
+ print_spd_info((unsigned char *)spd_data_ptr);
+
+ mem_cfg->MemorySpdDataLen = spd_data_len;
+ meminit_channels_dimm0(mem_cfg, board_cfg, spd_data_ptr,
+ half_populated);
+
+ /* LPDDR4 does not allow interleaved memory */
+ mem_cfg->DqPinsInterleaved = 0;
+ mem_cfg->ECT = board_cfg->ect;
+ mem_cfg->MrcSafeConfig = 0x1;
+}
diff --git a/src/soc/intel/jasperlake/p2sb.c b/src/soc/intel/jasperlake/p2sb.c
new file mode 100644
index 0000000000..64f181f634
--- /dev/null
+++ b/src/soc/intel/jasperlake/p2sb.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 3
+ */
+
+#include <console/console.h>
+#include <intelblocks/p2sb.h>
+
+void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
+{
+ uint32_t mask;
+
+ if (count != P2SB_EP_MASK_MAX_REG) {
+ printk(BIOS_ERR, "Unable to program EPMASK registers\n");
+ return;
+ }
+
+ /* Remove the host accessing right to PSF register range.
+ * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband
+ * access for PCI Root Bridge.
+ */
+ mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);
+
+ ep_mask[P2SB_EP_MASK_5_REG] = mask;
+
+ /*
+ * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband
+ * access for Broadcast and Multicast.
+ */
+ mask = (1 << 31) | (1 << 30);
+
+ ep_mask[P2SB_EP_MASK_7_REG] = mask;
+}
diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c
new file mode 100644
index 0000000000..13902b80a6
--- /dev/null
+++ b/src/soc/intel/jasperlake/pmc.c
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 4
+ */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <device/mmio.h>
+#include <device/device.h>
+#include <intelblocks/pmc.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/rtc.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/soc_chip.h>
+
+/*
+ * Set which power state system will be after reapplying
+ * the power (from G3 State)
+ */
+void pmc_soc_set_afterg3_en(const bool on)
+{
+ uint8_t reg8;
+ uint8_t *const pmcbase = pmc_mmio_regs();
+
+ reg8 = read8(pmcbase + GEN_PMCON_A);
+ if (on)
+ reg8 &= ~SLEEP_AFTER_POWER_FAIL;
+ else
+ reg8 |= SLEEP_AFTER_POWER_FAIL;
+ write8(pmcbase + GEN_PMCON_A, reg8);
+}
+
+static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
+{
+ uint32_t reg;
+ uint8_t *pmcbase = pmc_mmio_regs();
+
+ printk(BIOS_DEBUG, "%sabling Deep S%c\n",
+ enable ? "En" : "Dis", sx + '0');
+ reg = read32(pmcbase + offset);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ write32(pmcbase + offset, reg);
+}
+
+static void config_deep_s5(int on_ac, int on_dc)
+{
+ /* Treat S4 the same as S5. */
+ config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
+ config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
+ config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
+ config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
+}
+
+static void config_deep_s3(int on_ac, int on_dc)
+{
+ config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
+ config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
+}
+
+static void config_deep_sx(uint32_t deepsx_config)
+{
+ uint32_t reg;
+ uint8_t *pmcbase = pmc_mmio_regs();
+
+ reg = read32(pmcbase + DSX_CFG);
+ reg &= ~DSX_CFG_MASK;
+ reg |= deepsx_config;
+ write32(pmcbase + DSX_CFG, reg);
+}
+
+static void pmc_init(void *unused)
+{
+ const config_t *config = config_of_soc();
+
+ rtc_init();
+
+ pmc_set_power_failure_state(true);
+ pmc_gpe_init();
+
+ pmc_set_acpi_mode();
+
+ config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
+ config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
+ config_deep_sx(config->deep_sx_config);
+}
+
+/*
+* Initialize PMC controller.
+*
+* PMC controller gets hidden from PCI bus during FSP-Silicon init call.
+* Hence PCI enumeration can't be used to initialize bus device and
+* allocate resources.
+*/
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL);
diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c
new file mode 100644
index 0000000000..ac254020cb
--- /dev/null
+++ b/src/soc/intel/jasperlake/pmutil.c
@@ -0,0 +1,286 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Helper functions for dealing with power management registers
+ * and the differences between PCH variants.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 4
+ */
+
+
+#define __SIMPLE_DEVICE__
+
+#include <device/mmio.h>
+#include <cbmem.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <console/console.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/rtc.h>
+#include <intelblocks/tco.h>
+#include <soc/espi.h>
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/smbus.h>
+#include <soc/soc_chip.h>
+#include <security/vboot/vbnv.h>
+
+/*
+ * SMI
+ */
+
+const char *const *soc_smi_sts_array(size_t *a)
+{
+ static const char *const smi_sts_bits[] = {
+ [BIOS_STS_BIT] = "BIOS",
+ [LEGACY_USB_STS_BIT] = "LEGACY_USB",
+ [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
+ [APM_STS_BIT] = "APM",
+ [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
+ [PM1_STS_BIT] = "PM1",
+ [GPE0_STS_BIT] = "GPE0",
+ [GPIO_STS_BIT] = "GPI",
+ [MCSMI_STS_BIT] = "MCSMI",
+ [DEVMON_STS_BIT] = "DEVMON",
+ [TCO_STS_BIT] = "TCO",
+ [PERIODIC_STS_BIT] = "PERIODIC",
+ [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
+ [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
+ [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
+ [MONITOR_STS_BIT] = "MONITOR",
+ [SPI_SMI_STS_BIT] = "SPI",
+ [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
+ [ESPI_SMI_STS_BIT] = "ESPI_SMI",
+ };
+
+ *a = ARRAY_SIZE(smi_sts_bits);
+ return smi_sts_bits;
+}
+
+/*
+ * TCO
+ */
+
+const char *const *soc_tco_sts_array(size_t *a)
+{
+ static const char *const tco_sts_bits[] = {
+ [0] = "NMI2SMI",
+ [1] = "SW_TCO",
+ [2] = "TCO_INT",
+ [3] = "TIMEOUT",
+ [7] = "NEWCENTURY",
+ [8] = "BIOSWR",
+ [9] = "DMISCI",
+ [10] = "DMISMI",
+ [12] = "DMISERR",
+ [13] = "SLVSEL",
+ [16] = "INTRD_DET",
+ [17] = "SECOND_TO",
+ [18] = "BOOT",
+ [20] = "SMLINK_SLV"
+ };
+
+ *a = ARRAY_SIZE(tco_sts_bits);
+ return tco_sts_bits;
+}
+
+/*
+ * GPE0
+ */
+
+const char *const *soc_std_gpe_sts_array(size_t *a)
+{
+ static const char *const gpe_sts_bits[] = {
+ [1] = "HOTPLUG",
+ [2] = "SWGPE",
+ [6] = "TCO_SCI",
+ [7] = "SMB_WAK",
+ [9] = "PCI_EXP",
+ [10] = "BATLOW",
+ [11] = "PME",
+ [12] = "ME",
+ [13] = "PME_B0",
+ [14] = "eSPI",
+ [15] = "GPIO Tier-2",
+ [16] = "LAN_WAKE",
+ [18] = "WADT"
+ };
+
+ *a = ARRAY_SIZE(gpe_sts_bits);
+ return gpe_sts_bits;
+}
+
+void pmc_set_disb(void)
+{
+ /* Set the DISB after DRAM init */
+ uint8_t disb_val;
+ /* Only care about bits [23:16] of register GEN_PMCON_A */
+ uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
+
+ disb_val = read8(addr);
+ disb_val |= (DISB >> 16);
+
+ /* Don't clear bits that are write-1-to-clear */
+ disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
+ write8(addr, disb_val);
+}
+
+void pmc_clear_pmcon_sts(void)
+{
+ uint32_t reg_val;
+ uint8_t *addr;
+ addr = pmc_mmio_regs();
+
+ reg_val = read32(addr + GEN_PMCON_A);
+ /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
+ * while retaining MS4V write-1-to-clear bit */
+ reg_val &= ~(MS4V);
+
+ write32((addr + GEN_PMCON_A), reg_val);
+}
+
+/*
+ * PMC controller gets hidden from PCI bus
+ * during FSP-Silicon init call. Hence PWRMBASE
+ * can't be accessible using PCI configuration space
+ * read/write.
+ */
+uint8_t *pmc_mmio_regs(void)
+{
+ return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
+}
+
+uintptr_t soc_read_pmc_base(void)
+{
+ return (uintptr_t)pmc_mmio_regs();
+}
+
+
+uint32_t *soc_pmc_etr_addr(void)
+{
+ return (uint32_t *)(soc_read_pmc_base() + ETR);
+}
+
+void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
+{
+ DEVTREE_CONST struct soc_intel_tigerlake_config *config;
+
+ config = config_of_soc();
+
+ /* Assign to out variable */
+ *dw0 = config->pmc_gpe0_dw0;
+ *dw1 = config->pmc_gpe0_dw1;
+ *dw2 = config->pmc_gpe0_dw2;
+}
+
+static int rtc_failed(uint32_t gen_pmcon_b)
+{
+ return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
+}
+
+int soc_get_rtc_failed(void)
+{
+ const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+
+ if (!ps) {
+ printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n");
+ return 1;
+ }
+
+ return rtc_failed(ps->gen_pmcon_b);
+}
+
+int vbnv_cmos_failed(void)
+{
+ return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
+}
+
+static inline int deep_s3_enabled(void)
+{
+ uint32_t deep_s3_pol;
+
+ deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
+ return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
+}
+
+/* Return 0, 3, or 5 to indicate the previous sleep state. */
+int soc_prev_sleep_state(const struct chipset_power_state *ps,
+ int prev_sleep_state)
+{
+
+ /*
+ * Check for any power failure to determine if this a wake from
+ * S5 because the PCH does not set the WAK_STS bit when waking
+ * from a true G3 state.
+ */
+ if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
+ prev_sleep_state = ACPI_S5;
+
+ /*
+ * If waking from S3 determine if deep S3 is enabled. If not,
+ * need to check both deep sleep well and normal suspend well.
+ * Otherwise just check deep sleep well.
+ */
+ if (prev_sleep_state == ACPI_S3) {
+ /* PWR_FLR represents deep sleep power well loss. */
+ uint32_t mask = PWR_FLR;
+
+ /* If deep s3 isn't enabled check the suspend well too. */
+ if (!deep_s3_enabled())
+ mask |= SUS_PWR_FLR;
+
+ if (ps->gen_pmcon_a & mask)
+ prev_sleep_state = ACPI_S5;
+ }
+
+ return prev_sleep_state;
+}
+
+void soc_fill_power_state(struct chipset_power_state *ps)
+{
+ uint8_t *pmc;
+
+ ps->tco1_sts = tco_read_reg(TCO1_STS);
+ ps->tco2_sts = tco_read_reg(TCO2_STS);
+
+ printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
+ ps->tco1_sts, ps->tco2_sts);
+
+ pmc = pmc_mmio_regs();
+ ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
+ ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
+ ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
+ ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
+
+ printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
+ ps->gen_pmcon_a, ps->gen_pmcon_b);
+
+ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
+ ps->gblrst_cause[0], ps->gblrst_cause[1]);
+}
+
+/* STM Support */
+uint16_t get_pmbase(void)
+{
+ return (uint16_t) ACPI_BASE_ADDRESS;
+}
diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c
new file mode 100644
index 0000000000..431a70ccb0
--- /dev/null
+++ b/src/soc/intel/jasperlake/reset.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cf9_reset.h>
+#include <console/console.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/pmclib.h>
+#include <fsp/util.h>
+#include <soc/intel/common/reset.h>
+#include <soc/pci_devs.h>
+
+void do_global_reset(void)
+{
+ /* Ask CSE to do the global reset */
+ if (cse_request_global_reset(GLOBAL_RESET))
+ return;
+
+ /* global reset if CSE fail to reset */
+ pmc_global_reset_enable(1);
+ do_full_reset();
+}
+
+void chipset_handle_reset(uint32_t status)
+{
+ switch (status) {
+ case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
+ printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
+ global_reset();
+ break;
+ default:
+ printk(BIOS_ERR, "unhandled reset type %x\n", status);
+ die("unknown reset type");
+ break;
+ }
+}
diff --git a/src/soc/intel/jasperlake/romstage/Makefile.inc b/src/soc/intel/jasperlake/romstage/Makefile.inc
new file mode 100644
index 0000000000..ff32916433
--- /dev/null
+++ b/src/soc/intel/jasperlake/romstage/Makefile.inc
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += fsp_params_tgl.c
+romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += fsp_params_jsl.c
+romstage-y += ../../../../cpu/intel/car/romstage.c
+romstage-y += romstage.c
+romstage-y += pch.c
+romstage-y += systemagent.c
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params_jsl.c b/src/soc/intel/jasperlake/romstage/fsp_params_jsl.c
new file mode 100644
index 0000000000..18253aac9c
--- /dev/null
+++ b/src/soc/intel/jasperlake/romstage/fsp_params_jsl.c
@@ -0,0 +1,145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
+
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
+ const struct soc_intel_tigerlake_config *config)
+{
+ unsigned int i;
+ const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
+ uint32_t mask = 0;
+
+ if (!dev || !dev->enabled) {
+ /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */
+ m_cfg->InternalGfx = 0;
+ m_cfg->IgdDvmt50PreAlloc = 0;
+ } else {
+ m_cfg->InternalGfx = 1;
+ /* Set IGD stolen size to 60MB. */
+ m_cfg->IgdDvmt50PreAlloc = 0xFE;
+ }
+
+ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
+ m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
+ m_cfg->SaGv = config->SaGv;
+ m_cfg->RMT = config->RMT;
+
+ /* PCIe root port configuration */
+ for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
+ if (config->PcieRpEnable[i])
+ mask |= (1 << i);
+ }
+
+ m_cfg->PcieRpEnableMask = mask;
+
+ _Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcUsage) >=
+ ARRAY_SIZE(config->PcieClkSrcUsage), "copy buffer overflow!");
+ memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
+ sizeof(config->PcieClkSrcUsage));
+
+ _Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcClkReq) >=
+ ARRAY_SIZE(config->PcieClkSrcClkReq), "copy buffer overflow!");
+ memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
+ sizeof(config->PcieClkSrcClkReq));
+
+ m_cfg->PrmrrSize = config->PrmrrSize;
+ m_cfg->EnableC6Dram = config->enable_c6dram;
+
+ /* Disable BIOS Guard */
+ m_cfg->BiosGuard = 0;
+
+ /* Set CPU Ratio */
+ m_cfg->CpuRatio = 0;
+
+ /* Set debug interface flags */
+ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
+ DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO;
+
+ /* TraceHub configuration */
+ dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
+ if (dev && dev->enabled && config->TraceHubMode) {
+ m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB;
+ m_cfg->PchTraceHubMode = config->TraceHubMode;
+ m_cfg->CpuTraceHubMode = config->TraceHubMode;
+ }
+
+ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
+ m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
+
+
+ /* Enable SMBus controller based on config */
+ m_cfg->SmbusEnable = config->SmbusEnable;
+
+ /* Set debug probe type */
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT;
+
+ /* VT-d config */
+ m_cfg->VtdDisable = 0;
+
+ m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+
+ /* Display */
+ m_cfg->DdiPortAConfig = config->DdiPortAConfig;
+ m_cfg->DdiPortBHpd = config->DdiPortBHpd;
+ m_cfg->DdiPortCHpd = config->DdiPortCHpd;
+ m_cfg->DdiPortBDdc = config->DdiPortBDdc;
+ m_cfg->DdiPortCDdc = config->DdiPortCDdc;
+
+ /* Audio */
+ dev = pcidev_path_on_root(PCH_DEVFN_HDA);
+ if (!dev)
+ m_cfg->PchHdaEnable = 0;
+ else
+ m_cfg->PchHdaEnable = dev->enabled;
+
+ m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
+ m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
+
+ _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkDmicEnable) >=
+ ARRAY_SIZE(config->PchHdaAudioLinkDmicEnable), "copy buffer overflow!");
+ memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
+ sizeof(config->PchHdaAudioLinkDmicEnable));
+
+ _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSspEnable) >=
+ ARRAY_SIZE(config->PchHdaAudioLinkSspEnable), "copy buffer overflow!");
+ memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable,
+ sizeof(config->PchHdaAudioLinkSspEnable));
+
+ _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSndwEnable) >=
+ ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable), "copy buffer overflow!");
+ memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
+ sizeof(config->PchHdaAudioLinkSndwEnable));
+}
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+ const struct soc_intel_tigerlake_config *config = config_of_soc();
+ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+ soc_memory_init_params(m_cfg, config);
+
+ mainboard_memory_init_params(mupd);
+}
+
+__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c b/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c
new file mode 100644
index 0000000000..ac1a507270
--- /dev/null
+++ b/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c
@@ -0,0 +1,208 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <fsp/util.h>
+#include <soc/gpio_soc_defs.h>
+#include <soc/iomap.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
+
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
+ const struct soc_intel_tigerlake_config *config)
+{
+ unsigned int i;
+ uint32_t mask = 0;
+ const struct device *dev;
+
+ /* Set IGD stolen size to 60MB. */
+ m_cfg->IgdDvmt50PreAlloc = 0xFE;
+ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
+ m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
+ m_cfg->SaGv = config->SaGv;
+ m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
+ m_cfg->RMT = config->RMT;
+
+ /* CpuRatio Settings */
+ if (config->cpu_ratio_override) {
+ m_cfg->CpuRatio = config->cpu_ratio_override;
+ } else {
+ /* Set CpuRatio to match existing MSR value */
+ msr_t flex_ratio;
+ flex_ratio = rdmsr(MSR_FLEX_RATIO);
+ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
+ if (config->PcieRpEnable[i])
+ mask |= (1 << i);
+ }
+ m_cfg->PcieRpEnableMask = mask;
+
+ memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
+ sizeof(config->PcieClkSrcUsage));
+
+ for (i = 0; i < CONFIG_MAX_PCIE_CLOCKS; i++) {
+ if (config->PcieClkSrcUsage[i] == 0)
+ m_cfg->PcieClkSrcUsage[i] = 0xff;
+ }
+
+ memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
+ sizeof(config->PcieClkSrcClkReq));
+
+ m_cfg->PrmrrSize = config->PrmrrSize;
+ m_cfg->EnableC6Dram = config->enable_c6dram;
+ /* Disable BIOS Guard */
+ m_cfg->BiosGuard = 0;
+
+ /* UART Debug Log */
+ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
+ DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB :
+ DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB;
+ m_cfg->PcdIsaSerialUartBase = 0x0;
+ m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+
+ /*
+ * Skip IGD initialization in FSP if device
+ * is disable in devicetree.cb.
+ */
+ dev = pcidev_path_on_root(SA_DEVFN_IGD);
+ if (!dev || !dev->enabled)
+ m_cfg->InternalGfx = 0;
+ else
+ m_cfg->InternalGfx = 0x1;
+
+ /* ISH */
+ dev = pcidev_path_on_root(PCH_DEVFN_ISH);
+ if (!dev || !dev->enabled)
+ m_cfg->PchIshEnable = 0;
+ else
+ m_cfg->PchIshEnable = 1;
+
+ /* DP port config */
+ m_cfg->DdiPortAConfig = config->DdiPortAConfig;
+ m_cfg->DdiPortBConfig = config->DdiPortBConfig;
+ m_cfg->DdiPortAHpd = config->DdiPortAHpd;
+ m_cfg->DdiPortBHpd = config->DdiPortBHpd;
+ m_cfg->DdiPortCHpd = config->DdiPortCHpd;
+ m_cfg->DdiPort1Hpd = config->DdiPort1Hpd;
+ m_cfg->DdiPort2Hpd = config->DdiPort2Hpd;
+ m_cfg->DdiPort3Hpd = config->DdiPort3Hpd;
+ m_cfg->DdiPort4Hpd = config->DdiPort4Hpd;
+ m_cfg->DdiPortADdc = config->DdiPortADdc;
+ m_cfg->DdiPortBDdc = config->DdiPortBDdc;
+ m_cfg->DdiPortCDdc = config->DdiPortCDdc;
+ m_cfg->DdiPort1Ddc = config->DdiPort1Ddc;
+ m_cfg->DdiPort2Ddc = config->DdiPort2Ddc;
+ m_cfg->DdiPort3Ddc = config->DdiPort3Ddc;
+ m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;
+
+ /* Image clock: disable all clocks for bypassing FSP pin mux */
+ memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
+
+ /* Tcss */
+ m_cfg->TcssXhciEn = config->TcssXhciEn;
+ m_cfg->TcssXdciEn = config->TcssXdciEn;
+
+ /* USB4/TBT */
+ dev = pcidev_path_on_root(SA_DEVFN_TBT0);
+ if (dev)
+ m_cfg->TcssItbtPcie0En = dev->enabled;
+ else
+ m_cfg->TcssItbtPcie0En = 0;
+ dev = pcidev_path_on_root(SA_DEVFN_TBT1);
+ if (dev)
+ m_cfg->TcssItbtPcie1En = dev->enabled;
+ else
+ m_cfg->TcssItbtPcie1En = 0;
+
+ dev = pcidev_path_on_root(SA_DEVFN_TBT2);
+ if (dev)
+ m_cfg->TcssItbtPcie2En = dev->enabled;
+ else
+ m_cfg->TcssItbtPcie2En = 0;
+ dev = pcidev_path_on_root(SA_DEVFN_TBT3);
+ if (dev)
+ m_cfg->TcssItbtPcie3En = dev->enabled;
+ else
+ m_cfg->TcssItbtPcie3En = 0;
+
+ /* Enable Hyper Threading */
+ m_cfg->HyperThreading = 1;
+ /* Disable Lock PCU Thermal Management registers */
+ m_cfg->LockPTMregs = 0;
+ /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */
+ m_cfg->ChHashMask = 0x30CC;
+ /* Enable SMBus controller based on config */
+ m_cfg->SmbusEnable = config->SmbusEnable;
+ /* Set debug probe type */
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT;
+
+ /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
+ dev = pcidev_path_on_root(PCH_DEVFN_HDA);
+ if (!dev)
+ m_cfg->PchHdaEnable = 0;
+ else
+ m_cfg->PchHdaEnable = dev->enabled;
+
+ m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
+ m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
+ memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
+ sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
+ memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable,
+ sizeof(m_cfg->PchHdaAudioLinkSspEnable));
+ memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
+ sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
+ m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
+ m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
+ m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
+
+ /* Vt-D config */
+ m_cfg->VtdDisable = 0;
+ m_cfg->VtdIgdEnable = 0x1;
+ m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
+ m_cfg->VtdIpuEnable = 0x1;
+ m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
+ m_cfg->VtdIopEnable = 0x1;
+ m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS;
+ m_cfg->VtdItbtEnable = 0x1;
+ m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS;
+ m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS;
+ m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS;
+ m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS;
+
+ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
+ m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
+}
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+ const struct soc_intel_tigerlake_config *config;
+ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+ config = config_of_soc();
+
+ soc_memory_init_params(m_cfg, config);
+ mainboard_memory_init_params(mupd);
+}
+
+__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/soc/intel/jasperlake/romstage/pch.c b/src/soc/intel/jasperlake/romstage/pch.c
new file mode 100644
index 0000000000..a005ea0b99
--- /dev/null
+++ b/src/soc/intel/jasperlake/romstage/pch.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/smbus.h>
+#include <intelblocks/tco.h>
+#include <soc/romstage.h>
+
+void pch_init(void)
+{
+ /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
+ tco_configure();
+
+ /* Program SMBUS_BASE_ADDRESS and Enable it */
+ smbus_common_init();
+}
diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c
new file mode 100644
index 0000000000..f78ea29ae1
--- /dev/null
+++ b/src/soc/intel/jasperlake/romstage/romstage.c
@@ -0,0 +1,134 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/romstage.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <intelblocks/cfg.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/pmclib.h>
+#include <memory_info.h>
+#include <soc/intel/common/smbios.h>
+#include <soc/iomap.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
+
+#define FSP_SMBIOS_MEMORY_INFO_GUID \
+{ \
+ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
+ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
+}
+
+/* Save the DIMM information for SMBIOS table 17 */
+static void save_dimm_info(void)
+{
+ int node, channel, dimm, dimm_max, index;
+ size_t hob_size;
+ const CONTROLLER_INFO *ctrlr_info;
+ const CHANNEL_INFO *channel_info;
+ const DIMM_INFO *src_dimm;
+ struct dimm_info *dest_dimm;
+ struct memory_info *mem_info;
+ const MEMORY_INFO_DATA_HOB *meminfo_hob;
+ const uint8_t smbios_memory_info_guid[16] =
+ FSP_SMBIOS_MEMORY_INFO_GUID;
+ const uint8_t *serial_num;
+
+ /* Locate the memory info HOB, presence validated by raminit */
+ meminfo_hob = fsp_find_extension_hob_by_guid(
+ smbios_memory_info_guid,
+ &hob_size);
+ if (meminfo_hob == NULL || hob_size == 0) {
+ printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
+ return;
+ }
+
+ /*
+ * Allocate CBMEM area for DIMM information used to populate SMBIOS
+ * table 17
+ */
+ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+ if (mem_info == NULL) {
+ printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
+ return;
+ }
+ memset(mem_info, 0, sizeof(*mem_info));
+
+ /* Save available DIMM information */
+ index = 0;
+ dimm_max = ARRAY_SIZE(mem_info->dimm);
+ for (node = 0; node < MAX_NODE; node++) {
+ ctrlr_info = &meminfo_hob->Controller[node];
+ for (channel = 0; channel < MAX_CH && index < dimm_max;
+ channel++) {
+ channel_info = &ctrlr_info->ChannelInfo[channel];
+ if (channel_info->Status != CHANNEL_PRESENT)
+ continue;
+
+ for (dimm = 0; dimm < MAX_DIMM && index < dimm_max;
+ dimm++) {
+ src_dimm = &channel_info->DimmInfo[dimm];
+ dest_dimm = &mem_info->dimm[index];
+ if (src_dimm->Status != DIMM_PRESENT)
+ continue;
+
+ u8 memProfNum = meminfo_hob->MemoryProfile;
+ serial_num = src_dimm->SpdSave +
+ SPD_SAVE_OFFSET_SERIAL;
+
+ /* Populate the DIMM information */
+ dimm_info_fill(dest_dimm,
+ src_dimm->DimmCapacity,
+ meminfo_hob->MemoryType,
+ meminfo_hob->ConfiguredMemoryClockSpeed,
+ src_dimm->RankInDimm,
+ channel_info->ChannelId,
+ src_dimm->DimmId,
+ (const char *)src_dimm->ModulePartNum,
+ sizeof(src_dimm->ModulePartNum),
+ serial_num,
+ meminfo_hob->DataWidth,
+ meminfo_hob->VddVoltage[memProfNum],
+ meminfo_hob->EccSupport,
+ src_dimm->MfgId,
+ src_dimm->SpdModuleType);
+ index++;
+ }
+ }
+ }
+ mem_info->dimm_cnt = index;
+ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+}
+
+void mainboard_romstage_entry(void)
+{
+ bool s3wake;
+ struct chipset_power_state *ps = pmc_get_power_state();
+
+ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
+ systemagent_early_init();
+ /* Program PCH init */
+ pch_init();
+ /* initialize Heci interface */
+ heci_init(HECI1_BASE_ADDRESS);
+
+ s3wake = pmc_fill_power_state(ps) == ACPI_S3;
+ fsp_memory_init(s3wake);
+ pmc_set_disb();
+ if (!s3wake)
+ save_dimm_info();
+}
diff --git a/src/soc/intel/jasperlake/romstage/systemagent.c b/src/soc/intel/jasperlake/romstage/systemagent.c
new file mode 100644
index 0000000000..9fa498e802
--- /dev/null
+++ b/src/soc/intel/jasperlake/romstage/systemagent.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor SA Datasheet
+ * Document number: 571131
+ * Chapter number: 3
+ */
+
+#include <intelblocks/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/romstage.h>
+#include <soc/systemagent.h>
+
+void systemagent_early_init(void)
+{
+ static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
+ { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
+ { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
+ { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
+ };
+
+ static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = {
+ { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
+ { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
+ };
+
+ /* Set Fixed MMIO address into PCI configuration space */
+ sa_set_pci_bar(soc_fixed_pci_resources,
+ ARRAY_SIZE(soc_fixed_pci_resources));
+ /* Set Fixed MMIO address into MCH base address */
+ sa_set_mch_bar(soc_fixed_mch_resources,
+ ARRAY_SIZE(soc_fixed_mch_resources));
+ /* Enable PAM registers */
+ enable_pam_region();
+}
diff --git a/src/soc/intel/jasperlake/sd.c b/src/soc/intel/jasperlake/sd.c
new file mode 100644
index 0000000000..9898734f3d
--- /dev/null
+++ b/src/soc/intel/jasperlake/sd.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 26
+ */
+
+#include <intelblocks/sd.h>
+#include <soc/soc_chip.h>
+
+int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, struct device *dev)
+{
+ config_t *config = config_of(dev);
+
+ if (!config->sdcard_cd_gpio)
+ return -1;
+
+ gpio->type = ACPI_GPIO_TYPE_INTERRUPT;
+ gpio->pull = ACPI_GPIO_PULL_NONE;
+ gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
+ gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
+ gpio->irq.shared = ACPI_IRQ_SHARED;
+ gpio->irq.wake = ACPI_IRQ_WAKE;
+ gpio->interrupt_debounce_timeout = 10000; /* 100ms */
+ gpio->pin_count = 1;
+ gpio->pins[0] = config->sdcard_cd_gpio;
+
+ return 0;
+}
diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c
new file mode 100644
index 0000000000..67e59a26a0
--- /dev/null
+++ b/src/soc/intel/jasperlake/smihandler.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/smihandler.h>
+#include <soc/soc_chip.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+
+/*
+ * Specific SOC SMI handler during ramstage finalize phase
+ *
+ * BIOS can't make CSME function disable as is due to POSTBOOT_SAI
+ * restriction in place from TGP chipset. Hence create SMI Handler to
+ * perform CSME function disabling logic during SMM mode.
+ */
+void smihandler_soc_at_finalize(void)
+{
+ const struct soc_intel_tigerlake_config *config;
+
+ config = config_of_soc();
+
+ if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
+ heci_disable();
+}
+
+const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+ [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
+ [APM_STS_BIT] = smihandler_southbridge_apmc,
+ [PM1_STS_BIT] = smihandler_southbridge_pm1,
+ [GPE0_STS_BIT] = smihandler_southbridge_gpe0,
+ [GPIO_STS_BIT] = smihandler_southbridge_gpi,
+ [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
+ [MCSMI_STS_BIT] = smihandler_southbridge_mc,
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
+ [TCO_STS_BIT] = smihandler_southbridge_tco,
+#endif
+ [PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
+ [MONITOR_STS_BIT] = smihandler_southbridge_monitor,
+};
diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c
new file mode 100644
index 0000000000..44b464441d
--- /dev/null
+++ b/src/soc/intel/jasperlake/smmrelocate.c
@@ -0,0 +1,261 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
+#include <console/console.h>
+#include <smp/node.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <soc/soc_chip.h>
+#include <soc/systemagent.h>
+
+static void update_save_state(int cpu, uintptr_t curr_smbase,
+ uintptr_t staggered_smbase,
+ struct smm_relocation_params *relo_params)
+{
+ u32 smbase;
+ u32 iedbase;
+
+ /*
+ * The relocated handler runs with all CPUs concurrently. Therefore
+ * stagger the entry points adjusting SMBASE downwards by save state
+ * size * CPU num.
+ */
+ smbase = staggered_smbase;
+ iedbase = relo_params->ied_base;
+
+ printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
+ smbase, iedbase);
+
+ /*
+ * All threads need to set IEDBASE and SMBASE to the relocated
+ * handler region. However, the save state location depends on the
+ * smm_save_state_in_msrs field in the relocation parameters. If
+ * smm_save_state_in_msrs is non-zero then the CPUs are relocating
+ * the SMM handler in parallel, and each CPUs save state area is
+ * located in their respective MSR space. If smm_save_state_in_msrs
+ * is zero then the SMM relocation is happening serially so the
+ * save state is at the same default location for all CPUs.
+ */
+ if (relo_params->smm_save_state_in_msrs) {
+ msr_t smbase_msr;
+ msr_t iedbase_msr;
+
+ smbase_msr.lo = smbase;
+ smbase_msr.hi = 0;
+
+ /*
+ * According the BWG the IEDBASE MSR is in bits 63:32. It's
+ * not clear why it differs from the SMBASE MSR.
+ */
+ iedbase_msr.lo = 0;
+ iedbase_msr.hi = iedbase;
+
+ wrmsr(SMBASE_MSR, smbase_msr);
+ wrmsr(IEDBASE_MSR, iedbase_msr);
+ } else {
+ em64t101_smm_state_save_area_t *save_state;
+
+ save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
+ sizeof(*save_state));
+
+ save_state->smbase = smbase;
+ save_state->iedbase = iedbase;
+ }
+}
+
+/* Returns 1 if SMM MSR save state was set. */
+static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
+{
+ msr_t smm_mca_cap;
+
+ smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR);
+ if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) {
+ msr_t smm_feature_control;
+
+ smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);
+ smm_feature_control.hi = 0;
+ smm_feature_control.lo |= SMM_CPU_SAVE_EN;
+ wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
+ relo_params->smm_save_state_in_msrs = 1;
+ }
+ return relo_params->smm_save_state_in_msrs;
+}
+
+/*
+ * The relocation work is actually performed in SMM context, but the code
+ * resides in the ramstage module. This occurs by trampolining from the default
+ * SMRAM entry point to here.
+ */
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+ uintptr_t staggered_smbase)
+{
+ msr_t mtrr_cap;
+ struct smm_relocation_params *relo_params = &smm_reloc_params;
+
+ printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
+
+ /*
+ * Determine if the processor supports saving state in MSRs. If so,
+ * enable it before the non-BSPs run so that SMM relocation can occur
+ * in parallel in the non-BSP CPUs.
+ */
+ if (cpu == 0) {
+ /*
+ * If smm_save_state_in_msrs is 1 then that means this is the
+ * 2nd time through the relocation handler for the BSP.
+ * Parallel SMM handler relocation is taking place. However,
+ * it is desired to access other CPUs save state in the real
+ * SMM handler. Therefore, disable the SMM save state in MSRs
+ * feature.
+ */
+ if (relo_params->smm_save_state_in_msrs) {
+ msr_t smm_feature_control;
+
+ smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);
+ smm_feature_control.lo &= ~SMM_CPU_SAVE_EN;
+ wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
+ } else if (bsp_setup_msr_save_state(relo_params))
+ /*
+ * Just return from relocation handler if MSR save
+ * state is enabled. In that case the BSP will come
+ * back into the relocation handler to setup the new
+ * SMBASE as well disabling SMM save state in MSRs.
+ */
+ return;
+ }
+
+ /* Make appropriate changes to the save state map. */
+ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
+
+ /* Write SMRR MSRs based on indicated support. */
+ mtrr_cap = rdmsr(MTRR_CAP_MSR);
+ if (mtrr_cap.lo & SMRR_SUPPORTED)
+ write_smrr(relo_params);
+}
+
+static void fill_in_relocation_params(struct smm_relocation_params *params)
+{
+ uintptr_t tseg_base;
+ size_t tseg_size;
+ /* All range registers are aligned to 4KiB */
+ const u32 rmask = ~(4 * KiB - 1);
+
+ smm_region(&tseg_base, &tseg_size);
+
+ if (!IS_ALIGNED(tseg_base, tseg_size)) {
+ printk(BIOS_WARNING,
+ "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
+ return;
+ }
+
+ smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
+
+ /* SMRR has 32-bits of valid address aligned to 4KiB. */
+ params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
+ params->smrr_base.hi = 0;
+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
+ params->smrr_mask.hi = 0;
+}
+
+static void setup_ied_area(struct smm_relocation_params *params)
+{
+ char *ied_base;
+
+ struct ied_header ied = {
+ .signature = "INTEL RSVD",
+ .size = params->ied_size,
+ .reserved = {0},
+ };
+
+ ied_base = (void *)params->ied_base;
+
+ printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base);
+ printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size);
+
+ /* Place IED header at IEDBASE. */
+ memcpy(ied_base, &ied, sizeof(ied));
+
+ /* Zero out 32KiB at IEDBASE + 1MiB */
+ memset(ied_base + 1 * MiB, 0, 32 * KiB);
+}
+
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+ size_t *smm_save_state_size)
+{
+ printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
+
+ fill_in_relocation_params(&smm_reloc_params);
+
+ smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
+
+ if (smm_reloc_params.ied_size)
+ setup_ied_area(&smm_reloc_params);
+
+ *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
+}
+
+void smm_initialize(void)
+{
+ /* Clear the SMM state in the southbridge. */
+ smm_southbridge_clear_state();
+
+ /*
+ * Run the relocation handler for on the BSP to check and set up
+ * parallel SMM relocation.
+ */
+ smm_initiate_relocation();
+
+ if (smm_reloc_params.smm_save_state_in_msrs)
+ printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");
+}
+
+void smm_relocate(void)
+{
+ /*
+ * If smm_save_state_in_msrs is non-zero then parallel SMM relocation
+ * shall take place. Run the relocation handler a second time on the
+ * BSP to do * the final move. For APs, a relocation handler always
+ * needs to be run.
+ */
+ if (smm_reloc_params.smm_save_state_in_msrs)
+ smm_initiate_relocation_parallel();
+ else if (!boot_cpu())
+ smm_initiate_relocation();
+}
+
+void smm_lock(void)
+{
+ struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+ /*
+ * LOCK the SMM memory window and enable normal SMM.
+ * After running this function, only a full reset can
+ * make the SMM registers writable again.
+ */
+ printk(BIOS_DEBUG, "Locking SMM.\n");
+ pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
+}
diff --git a/src/soc/intel/jasperlake/spi.c b/src/soc/intel/jasperlake/spi.c
new file mode 100644
index 0000000000..5270616af6
--- /dev/null
+++ b/src/soc/intel/jasperlake/spi.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 7
+ */
+
+#include <intelblocks/spi.h>
+#include <soc/pci_devs.h>
+
+int spi_soc_devfn_to_bus(unsigned int devfn)
+{
+ switch (devfn) {
+ case PCH_DEVFN_SPI:
+ return 0;
+ case PCH_DEVFN_GSPI0:
+ return 1;
+ case PCH_DEVFN_GSPI1:
+ return 2;
+ case PCH_DEVFN_GSPI2:
+ return 3;
+ }
+ return -1;
+}
diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c
new file mode 100644
index 0000000000..fb0ce118aa
--- /dev/null
+++ b/src/soc/intel/jasperlake/systemagent.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor SA Datasheet
+ * Document number: 571131
+ * Chapter number: 3
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <intelblocks/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/systemagent.h>
+
+/*
+ * SoC implementation
+ *
+ * Add all known fixed memory ranges for Host Controller/Memory
+ * controller.
+ */
+void soc_add_fixed_mmio_resources(struct device *dev, int *index)
+{
+ static const struct sa_mmio_descriptor soc_fixed_resources[] = {
+ { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
+ "PCIEXBAR" },
+ { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
+ { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
+ { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
+ { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
+ { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
+ /*
+ * PMC pci device gets hidden from PCI bus due to Silicon
+ * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with
+ * SA resources to ensure that PMCBAR falls under PCI reserved
+ * memory range.
+ *
+ * Note: Don't add any more resource with same offset 0x10
+ * under this device space.
+ */
+ { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE,
+ "PMCBAR" },
+ };
+
+ sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
+ ARRAY_SIZE(soc_fixed_resources));
+
+ /* Add Vt-d resources if VT-d is enabled */
+ if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
+ return;
+
+ sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
+ ARRAY_SIZE(soc_vtd_resources));
+}
+
+/*
+ * SoC implementation
+ *
+ * Perform System Agent Initialization during Ramstage phase.
+ */
+void soc_systemagent_init(struct device *dev)
+{
+ /* Enable Power Aware Interrupt Routing */
+ enable_power_aware_intr();
+
+ /* Enable BIOS Reset CPL */
+ enable_bios_reset_cpl();
+}
diff --git a/src/soc/intel/jasperlake/uart.c b/src/soc/intel/jasperlake/uart.c
new file mode 100644
index 0000000000..03b4469a98
--- /dev/null
+++ b/src/soc/intel/jasperlake/uart.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 9
+ */
+
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <intelblocks/gpio.h>
+#include <intelblocks/lpss.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/uart.h>
+#include <soc/iomap.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+
+const struct uart_gpio_pad_config uart_gpio_pads[] = {
+ {
+ .console_index = 0,
+ .gpios = {
+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
+ },
+ },
+ {
+ .console_index = 1,
+ .gpios = {
+ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
+ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
+ },
+ },
+ {
+ .console_index = 2,
+ .gpios = {
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
+ },
+ }
+};
+
+const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
+
+DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
+{
+ /*
+ * if index is valid, this function will return corresponding structure
+ * for uart console else will return NULL.
+ */
+ switch (uart_console) {
+ case 0:
+ return pcidev_path_on_root(PCH_DEVFN_UART0);
+ case 1:
+ return pcidev_path_on_root(PCH_DEVFN_UART1);
+ case 2:
+ return pcidev_path_on_root(PCH_DEVFN_UART2);
+ default:
+ printk(BIOS_ERR, "Invalid UART console index\n");
+ return NULL;
+ }
+}