diff options
Diffstat (limited to 'src/soc/intel/quark/romstage/fsp2_0.c')
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index d03545d759..10e44c1b68 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -19,10 +19,12 @@ #include "../chip.h" #include <cpu/x86/cache.h> #include <fsp/util.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> #include <soc/reg_access.h> +#include <soc/storage_test.h> asmlinkage void *car_stage_c_entry(void) { @@ -34,6 +36,21 @@ asmlinkage void *car_stage_c_entry(void) post_code(0x20); console_init(); + if (IS_ENABLED(CONFIG_STORAGE_TEST)) { + uint32_t bar; + dev_t dev; + uint32_t previous_bar; + uint16_t previous_command; + + /* Enable the SD/MMC controller and run the test. Restore + * the BAR and command registers upon completion. + */ + dev = PCI_DEV(0, SD_MMC_DEV, SD_MMC_FUNC); + bar = storage_test_init(dev, &previous_bar, &previous_command); + storage_test(bar, 1); + storage_test_complete(dev, previous_bar, previous_command); + } + /* Initialize DRAM */ s3wake = fill_power_state() == ACPI_S3; fsp_memory_init(s3wake); |