diff options
Diffstat (limited to 'src/soc/intel/skylake/bootblock/cpu.c')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/cpu.c | 96 |
1 files changed, 71 insertions, 25 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 3a47d13f0a..d4506e592a 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <stdint.h> @@ -22,11 +23,18 @@ #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <device/pci_def.h> #include <arch/io.h> -#include <halt.h> #include <cpu/intel/microcode/microcode.c> -#include <soc/rcba.h> +#include <reset.h> #include <soc/msr.h> +#include <soc/pci_devs.h> +#include <soc/spi.h> + +/* Soft Reset Data Register Bit 12 = MAX Boot Frequency */ +#define SPI_STRAP_MAX_FREQ (1<<12) +/* Soft Reset Data Register Bit 6-11 = Flex Ratio */ +#define FLEX_RATIO_BIT 6 static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) @@ -47,7 +55,6 @@ static void enable_rom_caching(void) msr_t msr; disable_cache(); - /* Why only top 4MiB ? */ set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); enable_cache(); @@ -68,10 +75,59 @@ static void bootblock_mdelay(int ms) } while ((current.lo - start.lo) < target); } +static void set_pch_cpu_strap(u8 flex_ratio) +{ + device_t dev = PCH_DEV_SPI; + uint8_t *spibar = (void *)TEMP_SPI_BAR; + u32 ssl, ssms, soft_reset_data; + u8 pcireg; + + /* Assign Resources to SPI Controller */ + /* Clear BIT 1-2 SPI Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for SPI */ + pci_write_config32(dev, PCH_SPI_BASE_ADDRESS, TEMP_SPI_BAR); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Set Strap Lock Disable*/ + ssl = read32(spibar + SPIBAR_RESET_LOCK); + ssl |= SPIBAR_RESET_LOCK_DISABLE; + write32(spibar + SPIBAR_RESET_LOCK, ssl); + + /* Soft Reset Data Register Bit 12 = MAX Boot Frequency + * Bit 6-11 = Flex Ratio + * Soft Reset Data register located at SPIBAR0 offset 0xF8[0:15]. + */ + soft_reset_data = SPI_STRAP_MAX_FREQ; + soft_reset_data |= (flex_ratio << FLEX_RATIO_BIT); + write32(spibar + SPIBAR_RESET_DATA, soft_reset_data); + + /* Set Strap Mux Select set to '1' */ + ssms = read32(spibar + SPIBAR_RESET_CTRL); + ssms |= SPIBAR_RESET_CTRL_SSMC; + write32(spibar + SPIBAR_RESET_CTRL, ssms); + + /* Set Strap Lock Enable*/ + ssl = read32(spibar + SPIBAR_RESET_LOCK); + ssl |= SPIBAR_RESET_LOCK_ENABLE; + write32(spibar + SPIBAR_RESET_LOCK, ssl); + + /* Disable SPI Controller MMIO space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + static void set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; - u32 soft_reset; u8 nominal_ratio; /* Check for Flex Ratio support */ @@ -98,23 +154,14 @@ static void set_flex_ratio_to_tdp_nominal(void) flex_ratio.lo |= FLEX_RATIO_LOCK; wrmsr(MSR_FLEX_RATIO, flex_ratio); - /* Set flex ratio in soft reset data register bits 11:6. - * RCBA region is enabled in southbridge bootblock */ - soft_reset = RCBA32(SOFT_RESET_DATA); - soft_reset &= ~(0x3f << 6); - soft_reset |= (nominal_ratio & 0x3f) << 6; - RCBA32(SOFT_RESET_DATA) = soft_reset; - - /* Set soft reset control to use register value */ - RCBA32_OR(SOFT_RESET_CTRL, 1); + /* Set PCH Soft Reset Data Register with new Flex Ratio */ + set_pch_cpu_strap(nominal_ratio); /* Delay before reset to avoid potential TPM lockout */ bootblock_mdelay(30); - /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); + /* Issue soft reset, will be "CPU only" due to soft reset data */ + soft_reset(); } static void check_for_clean_reset(void) @@ -122,14 +169,13 @@ static void check_for_clean_reset(void) msr_t msr; msr = rdmsr(MTRRdefType_MSR); - /* Use the MTRR default type MSR as a proxy for detecting INIT#. + /* + * Use the MTRR default type MSR as a proxy for detecting INIT#. * Reset the system if any known bits are set in that MSR. That is - * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) { - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); - } + * an indication of the CPU not being properly reset. + */ + if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) + soft_reset(); } static void bootblock_cpu_init(void) |