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-rw-r--r--src/soc/intel/skylake/chip.c80
1 files changed, 80 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
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+++ b/src/soc/intel/skylake/chip.c
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+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/intel/broadwell/chip.h>
+
+static void pci_domain_set_resources(device_t dev)
+{
+ assign_resources(dev->link_list);
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = &pci_domain_read_resources,
+ .set_resources = &pci_domain_set_resources,
+ .scan_bus = &pci_domain_scan_bus,
+ .ops_pci_bus = &pci_bus_default_ops,
+};
+
+static struct device_operations cpu_bus_ops = {
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = &broadwell_init_cpus,
+};
+
+static void broadwell_enable(device_t dev)
+{
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ } else if (dev->path.type == DEVICE_PATH_PCI) {
+ /* Handle PCH device enable */
+ if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD &&
+ (dev->ops == NULL || dev->ops->enable == NULL)) {
+ broadwell_pch_enable_dev(dev);
+ }
+ }
+}
+
+struct chip_operations soc_intel_broadwell_ops = {
+ CHIP_NAME("Intel Broadwell")
+ .enable_dev = &broadwell_enable,
+ .init = &broadwell_init_pre_device,
+};
+
+static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device)
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ else
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ (device << 16) | vendor);
+}
+
+struct pci_operations broadwell_pci_ops = {
+ .set_subsystem = &pci_set_subsystem
+};