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path: root/src/soc/intel/skylake/chip_fsp20.c
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Diffstat (limited to 'src/soc/intel/skylake/chip_fsp20.c')
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index aad918a1ad..3bc66b2501 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -170,6 +170,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->PcieRpAdvancedErrorReporting));
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(params->PcieRpLtrEnable));
+ memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
+ sizeof(params->PcieRpHotPlug));
/*
* PcieRpClkSrcNumber UPD is set to clock source number(0-6) for