diff options
Diffstat (limited to 'src/soc/intel/skylake/chip_fsp20.c')
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 4cff6688a8..c5ecc97b01 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -203,6 +203,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownBiosInterface = config->LockDownConfigBiosInterface; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; + /* + * To disable HECI, the Psf needs to be left unlocked + * by FSP till end of post sequence. Based on the devicetree + * setting, we set the appropriate PsfUnlock policy in FSP, + * do the changes and then lock it back in coreboot during finalize. + */ + tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; + params->PchLockDownBiosLock = config->LockDownConfigBiosLock; params->PchLockDownSpiEiss = config->LockDownConfigSpiEiss; params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; |