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Diffstat (limited to 'src/soc/intel/skylake/chip_fsp20.c')
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 55fedd3cf5..c4f4e50cd2 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -28,6 +28,7 @@
#include <intelblocks/lpc_lib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/xdci.h>
+#include <intelblocks/p2sb.h>
#include <intelpch/lockdown.h>
#include <romstage_handoff.h>
#include <soc/acpi.h>
@@ -175,6 +176,13 @@ void soc_init_pre_device(void *chip_info)
/* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume());
+ /*
+ * Keep the P2SB device visible so it and the other devices are
+ * visible in coreboot for driver support and PCI resource allocation.
+ * There is no UPD setting for this.
+ */
+ p2sb_unhide();
+
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);