1 files changed, 0 insertions, 24 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 1682503d4b..6872c12101 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -21,7 +21,6 @@
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
-#include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/systemagent.h>
 
@@ -96,29 +95,6 @@ static void configure_c_states(void)
 	wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 }
 
-/*
- * The emulated ACPI timer allows disabling of the ACPI timer
- * (PM1_TMR) to have no impart on the system.
- */
-static void enable_pm_timer_emulation(void)
-{
-	msr_t msr;
-
-	if (!CONFIG_CPU_XTAL_HZ)
-		return;
-
-	/*
-	 * The derived frequency is calculated as follows:
-	 * (clock * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
-	 */
-	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
-	/* Set PM1 timer IO port and enable */
-	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
-			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
-	wrmsr(MSR_EMULATE_PM_TIMER, msr);
-}
-
 /* All CPUs including BSP will run the following function. */
 void soc_core_init(struct device *cpu)
 {