1 files changed, 38 insertions, 14 deletions

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 0e5d0931cc..600a15f3d9 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -42,6 +42,10 @@
 #include <soc/smm.h>
 #include <soc/systemagent.h>
 
+/* MP initialization support. */
+static const void *microcode_patch;
+static int ht_disabled;
+
 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
 static const u8 power_limit_time_sec_to_msr[] = {
 	[0]   = 0x00,
@@ -336,11 +340,10 @@ static void set_energy_perf_bias(u8 policy)
 static void configure_mca(void)
 {
 	msr_t msr;
-	const unsigned int mcg_cap_msr = 0x179;
 	int i;
 	int num_banks;
 
-	msr = rdmsr(mcg_cap_msr);
+	msr = rdmsr(IA32_MCG_CAP);
 	num_banks = msr.lo & 0xff;
 	msr.lo = msr.hi = 0;
 	/*
@@ -348,8 +351,13 @@ static void configure_mca(void)
 	 * of these banks are core vs package scope. For now every CPU clears
 	 * every bank.
 	 */
-	for (i = 0; i < num_banks; i++)
+	for (i = 0; i < num_banks; i++) {
+		/* Clear the machine check status */
 		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+		/* Initialize machine checks */
+		wrmsr(IA32_MC0_CTL + i * 4,
+			(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
+	}
 }
 
 /* All CPUs including BSP will run the following function. */
@@ -376,6 +384,9 @@ static void cpu_core_init(device_t cpu)
 
 	/* Enable Turbo */
 	enable_turbo();
+
+	/* Configure SGX */
+	configure_sgx(microcode_patch);
 }
 
 static struct device_operations cpu_dev_ops = {
@@ -399,10 +410,6 @@ static const struct cpu_driver driver __cpu_driver = {
 	.id_table = cpu_table,
 };
 
-/* MP initialization support. */
-static const void *microcode_patch;
-static int ht_disabled;
-
 static int get_cpu_count(void)
 {
 	msr_t msr;
@@ -500,6 +507,14 @@ static void soc_init_cpus(void *unused)
 
 	/* Thermal throttle activation offset */
 	configure_thermal_target();
+
+	/*
+	 * TODO: somehow calling configure_sgx() in cpu_core_init() is not
+	 * successful on the BSP (other threads are fine). Have to run it again
+	 * here to get SGX enabled on BSP. This behavior needs to root-caused
+	 * and we shall not have this redundant call.
+	 */
+	configure_sgx(microcode_patch);
 }
 
 /* Ensure to re-program all MTRRs based on DRAM resource settings */
@@ -511,16 +526,25 @@ static void soc_post_cpus_init(void *unused)
 
 int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
 {
-	msr_t msr;
-	/* If PRMRR/SGX is supported the FIT microcode load will set the msr
+	msr_t msr1;
+	msr_t msr2;
+
+	/*
+	 * If PRMRR/SGX is supported the FIT microcode load will set the msr
 	 * 0x08b with the Patch revision id one less than the id in the
 	 * microcode binary. The PRMRR support is indicated in the MSR
-	 * MTRRCAP[12]. Check for this feature and avoid reloading the
-	 * same microcode during CPU initialization.
+	 * MTRRCAP[12]. If SGX is not enabled, check and avoid reloading the
+	 * same microcode during CPU initialization. If SGX is enabled, as
+	 * part of SGX BIOS initialization steps, the same microcode needs to
+	 * be reloaded after the core PRMRR MSRs are programmed.
 	 */
-	msr = rdmsr(MTRR_CAP_MSR);
-	return (msr.lo & PRMRR_SUPPORTED)
-		&& (current_patch_id == new_patch_id - 1);
+	msr1 = rdmsr(MTRR_CAP_MSR);
+	msr2 = rdmsr(PRMRR_PHYS_BASE_MSR);
+	if (msr2.lo && (current_patch_id == new_patch_id - 1))
+		return 0;
+	else
+		return (msr1.lo & PRMRR_SUPPORTED) &&
+			(current_patch_id == new_patch_id - 1);
 }
 
 /*