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Diffstat (limited to 'src/soc/intel/skylake/fspcar.c')
-rw-r--r--src/soc/intel/skylake/fspcar.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c
index a4c3726492..0d27f57698 100644
--- a/src/soc/intel/skylake/fspcar.c
+++ b/src/soc/intel/skylake/fspcar.c
@@ -23,10 +23,19 @@ const FSPT_UPD temp_ram_init_params = {
.Reserved = {0},
},
.FsptCoreUpd = {
- .MicrocodeRegionBase =
- (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC,
- .MicrocodeRegionSize =
- (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN,
+ /*
+ * It is a requirement for firmware to have Firmware Interface Table
+ * (FIT), which contains pointers to each microcode update.
+ * The microcode update is loaded for all logical processors before
+ * cpu reset vector.
+ *
+ * All SoC since Gen-4 has above mechanism in place to load microcode
+ * even before hitting CPU reset vector. Hence skipping FSP-T loading
+ * microcode after CPU reset by passing '0' value to
+ * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
+ */
+ .MicrocodeRegionBase = 0,
+ .MicrocodeRegionLength = 0,
.CodeRegionBase =
(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,