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Diffstat (limited to 'src/soc/intel/skylake/graphics.c')
-rw-r--r--src/soc/intel/skylake/graphics.c35
1 files changed, 2 insertions, 33 deletions
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index dab7e145d1..d88709777a 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -1,16 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootmode.h>
+#include <acpi/acpi.h>
#include <commonlib/helpers.h>
#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
+#include <device/mmio.h>
#include <device/resource.h>
#include <drivers/intel/gma/i915.h>
#include <drivers/intel/gma/i915_reg.h>
-#include <drivers/intel/gma/libgfxinit.h>
#include <intelblocks/graphics.h>
-#include <drivers/intel/gma/opregion.h>
#include <soc/ramstage.h>
#include <types.h>
@@ -83,8 +80,6 @@ void graphics_soc_init(struct device *dev)
{
u32 ddi_buf_ctl;
- intel_gma_init_igd_opregion();
-
graphics_setup_panel(dev);
/*
@@ -97,32 +92,6 @@ void graphics_soc_init(struct device *dev)
ddi_buf_ctl |= DDI_A_4_LANES;
graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
}
-
- /* IGD needs to Bus Master */
- u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /*
- * GFX PEIM module inside FSP binary is taking care of graphics
- * initialization based on RUN_FSP_GOP Kconfig option and input
- * VBT file.
- *
- * In case of non-FSP solution, SoC need to select another
- * Kconfig to perform GFX initialization.
- */
- if (CONFIG(RUN_FSP_GOP)) {
- /* nothing to do */
- } else if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
- if (!acpi_is_wakeup_s3() && display_init_required()) {
- int lightup_ok;
- gma_gfxinit(&lightup_ok);
- gfx_set_init_done(lightup_ok);
- }
- } else {
- /* Initialize PCI device, load/execute BIOS Option ROM */
- pci_dev_init(dev);
- }
}
const struct i915_gpu_controller_info *