diff options
Diffstat (limited to 'src/soc/intel/skylake/include/soc/pm.h')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pm.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 54fc4a7f1d..3be83f4add 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,11 +15,11 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ -#ifndef _BROADWELL_PM_H_ -#define _BROADWELL_PM_H_ +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ /* ACPI_BASE_ADDRESS / PMBASE */ @@ -76,12 +77,6 @@ #define SWGPE_CTRL (1 << 1) #define DEVACT_STS 0x44 #define PM2_CNT 0x50 -#define TCO1_CNT 0x60 -#define TCO_TMR_HLT (1 << 11) -#define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) -#define TCO2_STS 0x66 -#define TCO2_STS_SECOND_TO (1 << 1) #define GPE0_REG_MAX 4 #define GPE0_REG_SIZE 32 @@ -102,7 +97,7 @@ #define SWGPE_STS (1 << 2) #define HOT_PLUG_STS (1 << 1) #define GPE0_EN(x) (0x90 + (x * 4)) -#define WADT_en (1 << 18) +#define WADT_EN (1 << 18) #define GP27_EN (1 << 16) #define PME_B0_EN (1 << 13) #define ME_SCI_EN (1 << 12) @@ -129,9 +124,8 @@ struct chipset_power_state { uint16_t tco2_sts; uint32_t gpe0_sts[4]; uint32_t gpe0_en[4]; - uint16_t gen_pmcon1; - uint16_t gen_pmcon2; - uint16_t gen_pmcon3; + uint16_t gen_pmcon_a; + uint16_t gen_pmcon_b; int prev_sleep_state; uint16_t hsio_version; uint16_t hsio_checksum; @@ -152,7 +146,8 @@ void disable_smi(uint32_t mask); /* ALT_GP_SMI */ uint32_t clear_alt_smi_status(void); -void enable_alt_smi(uint32_t mask); +void enable_alt_smi(int gpionum, u32 mask); +void reset_alt_smi_status(void); /* TCO */ uint32_t clear_tco_status(void); @@ -169,4 +164,9 @@ void disable_gpe(uint32_t mask); /* Return the selected ACPI SCI IRQ */ int acpi_sci_irq(void); +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); +/* Get base address of TCO I/O registers. */ +uint16_t pmc_tco_regs(void); + #endif |