3 files changed, 12 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/include/soc/lpc.h b/src/soc/intel/skylake/include/soc/lpc.h
index 58b78b0b72..b46b8ca5ca 100644
--- a/src/soc/intel/skylake/include/soc/lpc.h
+++ b/src/soc/intel/skylake/include/soc/lpc.h
@@ -50,6 +50,9 @@
 #define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
 #define LGMR			0x98 /* LPC Generic Memory Range */
 #define BIOS_CNTL		0xdc
+#define  LPC_BC_BILD		(1 << 7) /* BILD */
+#define  LPC_BC_LE		(1 << 2) /* LE */
+#define  LPC_BC_EISS		(1 << 5) /* EISS */
 #define PCCTL			0xE0 /* PCI Clock Control */
 #define CLKRUN_EN		(1 << 0)
 #endif
diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h
index bf3161b9ac..cb64af6578 100644
--- a/src/soc/intel/skylake/include/soc/pcr.h
+++ b/src/soc/intel/skylake/include/soc/pcr.h
@@ -31,11 +31,16 @@
 #define R_PCH_PCR_DMI_LPCLGIR2	0x2734
 #define R_PCH_PCR_DMI_LPCLGIR3	0x2738
 #define R_PCH_PCR_DMI_LPCLGIR4	0x273c
+#define R_PCH_PCR_DMI_GCS	0x274C
+#define B_PCH_PCR_DMI_GCS_BILD  (1 << 0)
 #define R_PCH_PCR_DMI_LPCIOD	0x2770
 #define R_PCH_PCR_DMI_LPCIOE	0x2774
 
 /* RTC configuration */
 #define R_PCH_PCR_RTC_CONF	0x3400
+#define B_PCH_PCR_RTC_CONF_UCMOS_LOCK             (1 << 4)
+#define B_PCH_PCR_RTC_CONF_LCMOS_LOCK             (1 << 3)
+#define B_PCH_PCR_RTC_CONF_RESERVED               (1 << 31)
 #define B_PCH_PCR_RTC_CONF_UCMOS_EN	0x4
 
 /* ITSS PCRs*/
diff --git a/src/soc/intel/skylake/include/soc/spi.h b/src/soc/intel/skylake/include/soc/spi.h
index a24197b3ec..7991c1632a 100644
--- a/src/soc/intel/skylake/include/soc/spi.h
+++ b/src/soc/intel/skylake/include/soc/spi.h
@@ -114,8 +114,11 @@
 #define  FLCOMP_C0DEN_32MB	6
 
 #define SPIBAR_BIOS_CNTL	0xDC
-#define  SPIBAR_BC_WPD		(1 << 0)
+#define  SPIBAR_BC_BILD		(1 << 7)
 #define  SPIBAR_BC_EISS		(1 << 5)
+#define  SPIBAR_BC_LE           (1 << 2)
+#define  SPIBAR_BC_WPD		(1 << 0)
+
 
 void *get_spi_bar(void);
 #endif