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-rw-r--r--src/soc/intel/skylake/include/fsp11/soc/romstage.h2
-rw-r--r--src/soc/intel/skylake/include/soc/pei_data.h89
-rw-r--r--src/soc/intel/skylake/include/soc/pei_wrapper.h27
3 files changed, 0 insertions, 118 deletions
diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
index 36825f7aea..386931043d 100644
--- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
@@ -24,6 +24,4 @@ void intel_early_me_status(void);
void enable_smbus(void);
int smbus_read_byte(unsigned int device, unsigned int address);
-void mainboard_fill_spd_data(struct pei_data *pei_data);
-
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h
deleted file mode 100644
index 5ea2190b8e..0000000000
--- a/src/soc/intel/skylake/include/soc/pei_data.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * UEFI PEI wrapper
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Google Inc. nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _PEI_DATA_H_
-#define _PEI_DATA_H_
-
-#include <types.h>
-
-#define PEI_VERSION 22
-
-#define ABI_X86 __attribute__((regparm(0)))
-
-typedef void ABI_X86(*tx_byte_func)(unsigned char byte);
-
-struct pei_data {
- uint32_t pei_version;
-
- int ec_present;
-
- /* Console output function */
- tx_byte_func tx_byte;
-
- /*
- * DIMM SPD data for memory down configurations
- * [CHANNEL][SLOT][SPD]
- */
- uint8_t spd_data[2][2][512];
-
- /*
- * LPDDR3 DQ byte map
- * [CHANNEL][ITERATION][2]
- *
- * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
- * DQByteMap[0] - ClkDQByteMap:
- * - If clock is per rank, program to [0xFF, 0xFF]
- * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
- * - If clock is shared by 2 ranks but does not go to all bytes,
- * Entry[i] defines which DQ bytes Group i services
- * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
- * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
- * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
- * For DDR, DQByteMap[3:1] = [0xFF, 0]
- * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
- * since we have 1 CTL / rank
- * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
- * since we have 1 CA Vref
- */
- uint8_t dq_map[2][12];
-
- /*
- * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
- * [CHANNEL][MAX_BYTES]
- */
- uint8_t dqs_map[2][8];
- uint16_t RcompResistor[3];
- uint16_t RcompTarget[5];
-
- int mem_cfg_id;
-} __packed;
-
-typedef struct pei_data PEI_DATA;
-
-#endif /* _PEI_DATA_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pei_wrapper.h b/src/soc/intel/skylake/include/soc/pei_wrapper.h
deleted file mode 100644
index d53fe8b769..0000000000
--- a/src/soc/intel/skylake/include/soc/pei_wrapper.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_PEI_WRAPPER_H_
-#define _SOC_PEI_WRAPPER_H_
-
-#include <soc/pei_data.h>
-
-typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data);
-
-void soc_fill_pei_data(struct pei_data *pei_data);
-void mainboard_fill_pei_data(struct pei_data *pei_data);
-
-#endif