diff options
Diffstat (limited to 'src/soc/intel/skylake/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index fb261c3c8b..cb704fd635 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> -#include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> #include <arch/cbfs.h> @@ -30,6 +28,7 @@ #include <device/pci.h> #include <device/pci_def.h> #include <elog.h> +#include <intelblocks/fast_spi.h> #include <reset.h> #include <romstage_handoff.h> #include <soc/pci_devs.h> @@ -38,8 +37,9 @@ #include <soc/pmc.h> #include <soc/serialio.h> #include <soc/romstage.h> -#include <soc/spi.h> #include <stage_cache.h> +#include <stddef.h> +#include <stdint.h> #include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -58,7 +58,7 @@ int get_sw_write_protect_state(void) u8 status; /* Return unprotected status if status read fails. */ - return early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80); + return fast_spi_flash_read_wpsr(&status) ? 0 : !!(status & 0x80); } /* UPD parameters to be initialized before MemoryInit */ |