diff options
Diffstat (limited to 'src/soc/intel/skylake/romstage/uart.c')
| -rw-r--r-- | src/soc/intel/skylake/romstage/uart.c | 78 |
1 files changed, 34 insertions, 44 deletions
diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c index 96c96343f1..8ddcbadda8 100644 --- a/src/soc/intel/skylake/romstage/uart.c +++ b/src/soc/intel/skylake/romstage/uart.c @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,72 +15,61 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ -#include <arch/early_variables.h> #include <arch/io.h> -#include <delay.h> #include <device/pci_def.h> -#include <reg_script.h> #include <stdint.h> -#include <uart8250.h> -#include <soc/iobp.h> +#include <soc/pci_devs.h> +#include <soc/pcr.h> +#include <soc/romstage.h> #include <soc/serialio.h> -const struct reg_script uart_init[] = { - /* Set MMIO BAR */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE), - /* Enable Memory access and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER), - /* Initialize LTR */ - REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_GEN, - ~SIO_REG_PPR_GEN_LTR_MODE_MASK, 0), - REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST, - ~(SIO_REG_PPR_RST_ASSERT), 0), - /* Take UART out of reset */ - REG_MMIO_OR32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST, - SIO_REG_PPR_RST_ASSERT), - /* Set M and N divisor inputs and enable clock */ - REG_MMIO_WRITE32(CONFIG_TTYS0_BASE + SIO_REG_PPR_CLOCK, - SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE | - (SIO_REG_PPR_CLOCK_N_DIV << 16) | - (SIO_REG_PPR_CLOCK_M_DIV << 1)), - REG_SCRIPT_END -}; - void pch_uart_init(void) { - /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ - u32 gpiodf = 0x131f; device_t dev; + u32 tmp, legacy; + u8 *base = (u8 *)CONFIG_TTYS0_BASE; - /* Put UART in byte access mode for 16550 compatibility */ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { case 0: dev = PCH_DEV_UART0; - gpiodf |= SIO_IOBP_GPIODF_UART0_BYTE_ACCESS; + legacy = SIO_PCH_LEGACY_UART0; break; case 1: dev = PCH_DEV_UART1; - gpiodf |= SIO_IOBP_GPIODF_UART1_BYTE_ACCESS; + legacy = SIO_PCH_LEGACY_UART1; + break; + case 2: + dev = PCH_DEV_UART2; + legacy = SIO_PCH_LEGACY_UART2; break; default: return; } - /* Program IOBP GPIODF */ - pch_iobp_update(SIO_IOBP_GPIODF, ~gpiodf, gpiodf); + /* Set configured UART base address */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base); - /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ - pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); + /* Enable memory access and bus master */ + tmp = pci_read_config32(dev, PCI_COMMAND); + tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, tmp); - /* Initialize chipset uart interface */ - reg_script_run_on_dev(dev, uart_init); + /* Take UART out of reset */ + tmp = read32(base + SIO_REG_PPR_RESETS); + tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | + SIO_REG_PPR_RESETS_IDMA; + write32(base + SIO_REG_PPR_RESETS, tmp); + + /* Set M and N divisor inputs and enable clock */ + tmp = read32(base + SIO_REG_PPR_CLOCK); + tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE | + (SIO_REG_PPR_CLOCK_N_DIV << 16) | + (SIO_REG_PPR_CLOCK_M_DIV << 1); + write32(base + SIO_REG_PPR_CLOCK, tmp); - /* - * Perform standard UART initialization - * Divisor 1 is 115200 BAUD - */ - uart8250_mem_init(CONFIG_TTYS0_BASE, 1); + /* Put UART in byte access mode for 16550 compatibility */ + pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, legacy); } |