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-rw-r--r--src/soc/intel/skylake/romstage/Makefile.inc13
-rw-r--r--src/soc/intel/skylake/romstage/cache_as_ram.inc341
-rw-r--r--src/soc/intel/skylake/romstage/cpu.c55
-rw-r--r--src/soc/intel/skylake/romstage/pch.c161
-rw-r--r--src/soc/intel/skylake/romstage/power_state.c132
-rw-r--r--src/soc/intel/skylake/romstage/raminit.c138
-rw-r--r--src/soc/intel/skylake/romstage/report_platform.c243
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c164
-rw-r--r--src/soc/intel/skylake/romstage/smbus.c54
-rw-r--r--src/soc/intel/skylake/romstage/spi.c149
-rw-r--r--src/soc/intel/skylake/romstage/stack.c124
-rw-r--r--src/soc/intel/skylake/romstage/systemagent.c55
-rw-r--r--src/soc/intel/skylake/romstage/uart.c85
13 files changed, 1714 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
new file mode 100644
index 0000000000..ae0f9806fd
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -0,0 +1,13 @@
+cpu_incs += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc
+
+romstage-y += cpu.c
+romstage-y += pch.c
+romstage-y += power_state.c
+romstage-y += raminit.c
+romstage-y += report_platform.c
+romstage-y += romstage.c
+romstage-y += smbus.c
+romstage-y += spi.c
+romstage-y += stack.c
+romstage-y += systemagent.c
+romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
diff --git a/src/soc/intel/skylake/romstage/cache_as_ram.inc b/src/soc/intel/skylake/romstage/cache_as_ram.inc
new file mode 100644
index 0000000000..a10ca4ca1b
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/cache_as_ram.inc
@@ -0,0 +1,341 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+#include <cbmem.h>
+
+/* The full cache-as-ram size includes the cache-as-ram portion from coreboot
+ * and the space used by the reference code. These 2 values combined should
+ * be a power of 2 because the MTRR setup assumes that. */
+#define CACHE_AS_RAM_SIZE \
+ (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+#define CACHE_AS_RAM_LIMIT (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)
+#define USBDEBUG_VAR_SIZE 36 /* sizeof(struct ehci_debug_info) */
+
+/* Cache 4GB - MRC_SIZE_KB for MRC */
+#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
+#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
+#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
+
+#define CPU_MAXPHYSADDR CONFIG_CPU_ADDR_BITS
+#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1)
+
+#define NoEvictMod_MSR 0x2e0
+
+ /* Save the BIST result. */
+ movl %eax, %ebp
+
+cache_as_ram:
+ post_code(0x20)
+
+ /* Send INIT IPI to all excluding ourself. */
+ movl $0x000C4500, %eax
+ movl $0xFEE00300, %esi
+ movl %eax, (%esi)
+
+ /* All CPUs need to be in Wait for SIPI state */
+wait_for_sipi:
+ movl (%esi), %eax
+ bt $12, %eax
+ jc wait_for_sipi
+
+ post_code(0x21)
+ /* Zero out all fixed range and variable range MTRRs. */
+ movl $mtrr_table, %esi
+ movl $((mtrr_table_end - mtrr_table) / 2), %edi
+ xorl %eax, %eax
+ xorl %edx, %edx
+clear_mtrrs:
+ movw (%esi), %bx
+ movzx %bx, %ecx
+ wrmsr
+ add $2, %esi
+ dec %edi
+ jnz clear_mtrrs
+
+ post_code(0x22)
+ /* Configure the default memory type to uncacheable. */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ andl $(~0x00000cff), %eax
+ wrmsr
+
+ post_code(0x23)
+ /* Set Cache-as-RAM base address. */
+ movl $(MTRRphysBase_MSR(0)), %ecx
+ movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+ xorl %edx, %edx
+ wrmsr
+
+ post_code(0x24)
+ /* Set Cache-as-RAM mask. */
+ movl $(MTRRphysMask_MSR(0)), %ecx
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $CPU_PHYSMASK_HI, %edx
+ wrmsr
+
+ post_code(0x25)
+
+ /* Enable MTRR. */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ orl $MTRRdefTypeEn, %eax
+ wrmsr
+
+ /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+ movl %cr0, %eax
+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+ invd
+ movl %eax, %cr0
+
+ /* enable the 'no eviction' mode */
+ movl $NoEvictMod_MSR, %ecx
+ rdmsr
+ orl $1, %eax
+ andl $~2, %eax
+ wrmsr
+
+ /* Clear the cache memory region. This will also fill up the cache */
+ movl $CACHE_AS_RAM_BASE, %esi
+ movl %esi, %edi
+ movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ xorl %eax, %eax
+ rep stosl
+
+ /* enable the 'no eviction run' state */
+ movl $NoEvictMod_MSR, %ecx
+ rdmsr
+ orl $3, %eax
+ wrmsr
+
+ post_code(0x26)
+ /* Enable Cache-as-RAM mode by disabling cache. */
+ movl %cr0, %eax
+ orl $CR0_CacheDisable, %eax
+ movl %eax, %cr0
+
+ /* Enable cache for our code in Flash because we do XIP here */
+ movl $MTRRphysBase_MSR(1), %ecx
+ xorl %edx, %edx
+ /*
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
+ * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ */
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ orl $MTRR_TYPE_WRPROT, %eax
+ wrmsr
+
+ movl $MTRRphysMask_MSR(1), %ecx
+ movl $CPU_PHYSMASK_HI, %edx
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ wrmsr
+
+ post_code(0x27)
+#if CONFIG_CACHE_MRC_BIN
+ /* Enable caching for ram init code to run faster */
+ movl $MTRRphysBase_MSR(2), %ecx
+ movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
+ xorl %edx, %edx
+ wrmsr
+ movl $MTRRphysMask_MSR(2), %ecx
+ movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+ movl $CPU_PHYSMASK_HI, %edx
+ wrmsr
+#endif
+
+ post_code(0x28)
+ /* Enable cache. */
+ movl %cr0, %eax
+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+ movl %eax, %cr0
+
+ /* Setup the stack. */
+ movl $(CACHE_AS_RAM_LIMIT), %eax
+#if CONFIG_USBDEBUG
+ sub $(USBDEBUG_VAR_SIZE), %eax
+#endif
+ movl %eax, %esp
+
+ /* Restore the BIST result. */
+ movl %ebp, %eax
+
+ /* Build the call frame. */
+ movl %esp, %ebp
+ movd %mm1, %ebx
+ pushl %ebx
+ movd %mm0, %ebx
+ pushl %ebx
+ pushl %eax
+
+before_romstage:
+ post_code(0x29)
+ /* Call romstage.c main function. */
+ call romstage_main
+ /* Save return value from romstage_main. It contains the stack to use
+ * after cache-as-ram is torn down. It also contains the information
+ * for setting up MTRRs. */
+ movl %eax, %ebx
+
+ post_code(0x2f)
+
+ /* Copy global variable space (for USBDEBUG) to memory */
+#if CONFIG_USBDEBUG
+ cld
+ movl $(CACHE_AS_RAM_LIMIT - USBDEBUG_VAR_SIZE), %esi
+ movl $(CONFIG_RAMTOP - USBDEBUG_VAR_SIZE), %edi
+ movl $USBDEBUG_VAR_SIZE, %ecx
+ rep movsb
+#endif
+
+ post_code(0x30)
+
+ /* Disable cache. */
+ movl %cr0, %eax
+ orl $CR0_CacheDisable, %eax
+ movl %eax, %cr0
+
+ post_code(0x31)
+
+ /* Disable MTRR. */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ andl $(~MTRRdefTypeEn), %eax
+ wrmsr
+
+ post_code(0x31)
+
+ /* Disable the no eviction run state */
+ movl $NoEvictMod_MSR, %ecx
+ rdmsr
+ andl $~2, %eax
+ wrmsr
+
+ invd
+
+ /* Disable the no eviction mode */
+ rdmsr
+ andl $~1, %eax
+ wrmsr
+
+#if CONFIG_CACHE_MRC_BIN
+ /* Clear MTRR that was used to cache MRC */
+ xorl %eax, %eax
+ xorl %edx, %edx
+ movl $MTRRphysBase_MSR(2), %ecx
+ wrmsr
+ movl $MTRRphysMask_MSR(2), %ecx
+ wrmsr
+#endif
+
+ post_code(0x33)
+
+ /* Enable cache. */
+ movl %cr0, %eax
+ andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+ movl %eax, %cr0
+
+ post_code(0x36)
+
+ /* Disable cache. */
+ movl %cr0, %eax
+ orl $CR0_CacheDisable, %eax
+ movl %eax, %cr0
+
+ post_code(0x38)
+
+ /* Setup stack as indicated by return value from ramstage_main(). */
+ movl %ebx, %esp
+
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRRphysBase_MSR(0), %ecx
+1:
+ testl %ebx, %ebx
+ jz 1f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
+ wrmsr
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
+ wrmsr
+ inc %ecx
+
+ dec %ebx
+ jmp 1b
+1:
+ post_code(0x39)
+
+ /* And enable cache again after setting MTRRs. */
+ movl %cr0, %eax
+ andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+ movl %eax, %cr0
+
+ post_code(0x3a)
+
+ /* Enable MTRR. */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ orl $MTRRdefTypeEn, %eax
+ wrmsr
+
+ post_code(0x3b)
+
+ /* Invalidate the cache again. */
+ invd
+
+ post_code(0x3c)
+
+__main:
+ post_code(POST_PREPARE_RAMSTAGE)
+ cld /* Clear direction flag. */
+ call romstage_after_car
+
+.Lhlt:
+ post_code(POST_DEAD_CODE)
+ hlt
+ jmp .Lhlt
+
+mtrr_table:
+ /* Fixed MTRRs */
+ .word 0x250, 0x258, 0x259
+ .word 0x268, 0x269, 0x26A
+ .word 0x26B, 0x26C, 0x26D
+ .word 0x26E, 0x26F
+ /* Variable MTRRs */
+ .word 0x200, 0x201, 0x202, 0x203
+ .word 0x204, 0x205, 0x206, 0x207
+ .word 0x208, 0x209, 0x20A, 0x20B
+ .word 0x20C, 0x20D, 0x20E, 0x20F
+ .word 0x210, 0x211, 0x212, 0x213
+mtrr_table_end:
+
diff --git a/src/soc/intel/skylake/romstage/cpu.c b/src/soc/intel/skylake/romstage/cpu.c
new file mode 100644
index 0000000000..af175be86f
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/cpu.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cpu.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/romstage.h>
+
+u32 cpu_family_model(void)
+{
+ return cpuid_eax(1) & 0x0fff0ff0;
+}
+
+void set_max_freq(void)
+{
+ msr_t msr, perf_ctl, platform_info;
+
+ /* Check for configurable TDP option */
+ platform_info = rdmsr(MSR_PLATFORM_INFO);
+
+ if ((platform_info.hi >> 1) & 3) {
+ /* Set to nominal TDP ratio */
+ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+ perf_ctl.lo = (msr.lo & 0xff) << 8;
+ } else {
+ /* Platform Info bits 15:8 give max ratio */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ perf_ctl.lo = msr.lo & 0xff00;
+ }
+
+ perf_ctl.hi = 0;
+ wrmsr(IA32_PERF_CTL, perf_ctl);
+
+ printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
+ ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+}
diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c
new file mode 100644
index 0000000000..6fa6c395e2
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/pch.c
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <reg_script.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/rcba.h>
+#include <soc/romstage.h>
+#include <soc/smbus.h>
+#include <soc/intel/broadwell/chip.h>
+
+const struct reg_script pch_early_init_script[] = {
+ /* Setup southbridge BARs */
+ REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1),
+ REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1),
+ REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),
+ REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),
+ REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),
+
+ /* Set COM1/COM2 decode range */
+ REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),
+ /* Enable legacy decode ranges */
+ REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
+ COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),
+
+ /* Enable IOAPIC */
+ REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),
+ /* Read back for posted write */
+ REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),
+
+ /* Set HPET address and enable it */
+ REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),
+ /* Read back for posted write */
+ REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),
+ /* Enable HPET to start counter */
+ REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),
+
+ /* Disable reset */
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)),
+ /* TCO timer halt */
+ REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),
+
+ /* Enable upper 128 bytes of CMOS */
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)),
+
+ /* Disable unused device (always) */
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS),
+
+ REG_SCRIPT_END
+};
+
+const struct reg_script pch_interrupt_init_script[] = {
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D28IP_P1IP PCIE INTA -> PIRQA
+ * D29IP_E1P EHCI INTA -> PIRQD
+ * D20IP_XHCI XHCI INTA -> PIRQC (MSI)
+ * D31IP_SIP SATA INTA -> PIRQF (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQG
+ * D31IP_TTIP THRT INTC -> PIRQA
+ * D27IP_ZIP HDA INTA -> PIRQG (MSI)
+ */
+
+ /* Device interrupt pin register (board specific) */
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IP,
+ (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IP, (INTA << D29IP_E1P)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IP,
+ (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+ (INTB << D28IP_P4IP)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IP, (INTA << D27IP_ZIP)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D26IP, (INTA << D26IP_E2P)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IP, (NOINT << D22IP_MEI1IP)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IP, (INTA << D20IP_XHCI)),
+
+ /* Device interrupt route registers */
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IR, /* LPC */
+ DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IR, /* EHCI */
+ DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IR, /* PCIE */
+ DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IR, /* HDA */
+ DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IR, /* ME */
+ DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D21IR, /* SIO */
+ DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IR, /* XHCI */
+ DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D23IR, /* SDIO */
+ DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),
+
+ REG_SCRIPT_END
+};
+
+static void pch_enable_lpc(void)
+{
+ /* Lookup device tree in romstage */
+ const struct device *dev;
+ const config_t *config;
+
+ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+ if (!dev || !dev->chip_info)
+ return;
+ config = dev->chip_info;
+
+ pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
+ pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);
+ pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec);
+ pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec);
+}
+
+static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
+{
+ u32 reg32;
+
+ reg32 = pci_read_config32(dev, reg);
+ reg32 &= mask;
+ reg32 |= or;
+ pci_write_config32(dev, reg, reg32);
+}
+
+void pch_early_init(void)
+{
+ reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);
+ reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script);
+
+ pch_enable_lpc();
+
+ enable_smbus();
+
+ /* 8.14 Additional PCI Express Programming Steps, step #1 */
+ pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0);
+ pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80);
+ pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30);
+}
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
new file mode 100644
index 0000000000..bdb3da9c3b
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -0,0 +1,132 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/early_variables.h>
+#include <arch/io.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <reg_script.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
+
+static struct chipset_power_state power_state CAR_GLOBAL;
+
+static void migrate_power_state(void)
+{
+ struct chipset_power_state *ps_cbmem;
+ struct chipset_power_state *ps_car;
+
+ ps_car = car_get_var_ptr(&power_state);
+ ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem));
+
+ if (ps_cbmem == NULL) {
+ printk(BIOS_DEBUG, "Not adding power state to cbmem!\n");
+ return;
+ }
+ memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
+}
+CAR_MIGRATE(migrate_power_state);
+
+/* Return 0, 3, or 5 to indicate the previous sleep state. */
+static int prev_sleep_state(struct chipset_power_state *ps)
+{
+ /* Default to S0. */
+ int prev_sleep_state = SLEEP_STATE_S0;
+
+ if (ps->pm1_sts & WAK_STS) {
+ switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
+#if CONFIG_HAVE_ACPI_RESUME
+ case SLP_TYP_S3:
+ prev_sleep_state = SLEEP_STATE_S3;
+ break;
+#endif
+ case SLP_TYP_S5:
+ prev_sleep_state = SLEEP_STATE_S5;
+ break;
+ }
+ /* Clear SLP_TYP. */
+ outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
+ }
+
+ if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
+ prev_sleep_state = SLEEP_STATE_S5;
+
+ return prev_sleep_state;
+}
+
+static void dump_power_state(struct chipset_power_state *ps)
+{
+ printk(BIOS_DEBUG, "PM1_STS: %04x\n", ps->pm1_sts);
+ printk(BIOS_DEBUG, "PM1_EN: %04x\n", ps->pm1_en);
+ printk(BIOS_DEBUG, "PM1_CNT: %08x\n", ps->pm1_cnt);
+ printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
+ ps->tco1_sts, ps->tco2_sts);
+
+ printk(BIOS_DEBUG, "GPE0_STS: %08x %08x %08x %08x\n",
+ ps->gpe0_sts[0], ps->gpe0_sts[1],
+ ps->gpe0_sts[2], ps->gpe0_sts[3]);
+ printk(BIOS_DEBUG, "GPE0_EN: %08x %08x %08x %08x\n",
+ ps->gpe0_en[0], ps->gpe0_en[1],
+ ps->gpe0_en[2], ps->gpe0_en[3]);
+
+ printk(BIOS_DEBUG, "GEN_PMCON: %04x %04x %04x\n",
+ ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
+
+ printk(BIOS_DEBUG, "Previous Sleep State: S%d\n",
+ ps->prev_sleep_state);
+}
+
+/* Fill power state structure from ACPI PM registers */
+struct chipset_power_state *fill_power_state(void)
+{
+ struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+
+ ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
+ ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
+ ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+ ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
+ ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
+ ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
+ ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
+ ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
+ ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
+ ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
+ ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
+ ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
+ ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
+
+ ps->gen_pmcon1 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_1);
+ ps->gen_pmcon2 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_2);
+ ps->gen_pmcon3 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_3);
+
+ ps->prev_sleep_state = prev_sleep_state(ps);
+
+ dump_power_state(ps);
+
+ return ps;
+}
diff --git a/src/soc/intel/skylake/romstage/raminit.c b/src/soc/intel/skylake/romstage/raminit.c
new file mode 100644
index 0000000000..52ea49100d
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/raminit.c
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cbfs.h>
+#include <arch/io.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <lib.h>
+#include <string.h>
+#if CONFIG_EC_GOOGLE_CHROMEEC
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#endif
+#include <stage_cache.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/intel/common/mrc_cache.h>
+#include <soc/iomap.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/pm.h>
+#include <soc/reset.h>
+#include <soc/romstage.h>
+#include <soc/smm.h>
+#include <soc/systemagent.h>
+
+/*
+ * Find PEI executable in coreboot filesystem and execute it.
+ */
+void raminit(struct pei_data *pei_data)
+{
+ const struct mrc_saved_data *cache;
+ struct memory_info* mem_info;
+ pei_wrapper_entry_t entry;
+ int ret;
+
+ broadwell_fill_pei_data(pei_data);
+
+ if (recovery_mode_enabled()) {
+ /* Recovery mode does not use MRC cache */
+ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n");
+ } else if (!mrc_cache_get_current(&cache)) {
+ /* MRC cache found */
+ pei_data->saved_data_size = cache->size;
+ pei_data->saved_data = &cache->data[0];
+ } else if (pei_data->boot_mode == SLEEP_STATE_S3) {
+ /* Waking from S3 and no cache. */
+ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
+ post_code(POST_RESUME_FAILURE);
+ reset_system();
+ } else {
+ printk(BIOS_DEBUG, "No MRC cache found.\n");
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ if (pei_data->boot_mode == SLEEP_STATE_S0) {
+ /* Ensure EC is running RO firmware. */
+ google_chromeec_check_ec_image(EC_IMAGE_RO);
+ }
+#endif
+ }
+
+ /*
+ * Do not use saved pei data. Can be set by mainboard romstage
+ * to force a full train of memory on every boot.
+ */
+ if (pei_data->disable_saved_data) {
+ printk(BIOS_DEBUG, "Disabling PEI saved data by request\n");
+ pei_data->saved_data = NULL;
+ pei_data->saved_data_size = 0;
+ }
+
+ /* Determine if mrc.bin is in the cbfs. */
+ entry = (pei_wrapper_entry_t)cbfs_get_file_content(
+ CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, NULL);
+ if (entry == NULL) {
+ printk(BIOS_DEBUG, "Couldn't find mrc.bin\n");
+ return;
+ }
+
+ printk(BIOS_DEBUG, "Starting Memory Reference Code\n");
+
+ ret = entry(pei_data);
+ if (ret < 0)
+ die("pei_data version mismatch\n");
+
+ /* Print the MRC version after executing the UEFI PEI stage. */
+ u32 version = MCHBAR32(MCHBAR_PEI_VERSION);
+ printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n",
+ version >> 24 , (version >> 16) & 0xff,
+ (version >> 8) & 0xff, version & 0xff);
+
+ report_memory_config();
+
+ /* Basic memory sanity test */
+ quick_ram_check();
+
+ if (pei_data->boot_mode != SLEEP_STATE_S3) {
+ cbmem_initialize_empty();
+ stage_cache_create_empty();
+ } else {
+ stage_cache_recover();
+ if (cbmem_initialize()) {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+ /* Failed S3 resume, reset to come up cleanly */
+ reset_system();
+#endif
+ }
+ }
+
+ printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
+ pei_data->data_to_save_size);
+
+ if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0)
+ mrc_cache_stash_data(pei_data->data_to_save,
+ pei_data->data_to_save_size);
+
+ printk(BIOS_DEBUG, "create cbmem for dimm information\n");
+ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
+ memcpy(mem_info, &pei_data->meminfo, sizeof(struct memory_info));
+
+}
diff --git a/src/soc/intel/skylake/romstage/report_platform.c b/src/soc/intel/skylake/romstage/report_platform.c
new file mode 100644
index 0000000000..713b3e7abf
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/report_platform.c
@@ -0,0 +1,243 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/x86/msr.h>
+#include <soc/cpu.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/systemagent.h>
+
+static struct {
+ u32 cpuid;
+ const char *name;
+} cpu_table[] = {
+ { CPUID_HASWELL_A0, "Haswell A0" },
+ { CPUID_HASWELL_B0, "Haswell B0" },
+ { CPUID_HASWELL_C0, "Haswell C0" },
+ { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" },
+ { CPUID_HASWELL_ULT, "Haswell ULT C0 or D0" },
+ { CPUID_HASWELL_HALO, "Haswell Perf Halo" },
+ { CPUID_BROADWELL_C0, "Broadwell C0" },
+ { CPUID_BROADWELL_D0, "Broadwell D0" },
+ { CPUID_BROADWELL_E0, "Broadwell E0 or F0" },
+};
+
+static struct {
+ u8 revid;
+ const char *name;
+} mch_rev_table[] = {
+ { MCH_BROADWELL_REV_D0, "Broadwell D0" },
+ { MCH_BROADWELL_REV_E0, "Broadwell E0" },
+ { MCH_BROADWELL_REV_F0, "Broadwell F0" },
+};
+
+static struct {
+ u16 lpcid;
+ const char *name;
+} pch_table[] = {
+ { PCH_LPT_LP_SAMPLE, "LynxPoint LP Sample" },
+ { PCH_LPT_LP_PREMIUM, "LynxPoint LP Premium" },
+ { PCH_LPT_LP_MAINSTREAM, "LynxPoint LP Mainstream" },
+ { PCH_LPT_LP_VALUE, "LynxPoint LP Value" },
+ { PCH_WPT_HSW_U_SAMPLE, "Haswell U Sample" },
+ { PCH_WPT_BDW_U_SAMPLE, "Broadwell U Sample" },
+ { PCH_WPT_BDW_U_PREMIUM, "Broadwell U Premium" },
+ { PCH_WPT_BDW_U_BASE, "Broadwell U Base" },
+ { PCH_WPT_BDW_Y_SAMPLE, "Broadwell Y Sample" },
+ { PCH_WPT_BDW_Y_PREMIUM, "Broadwell Y Premium" },
+ { PCH_WPT_BDW_Y_BASE, "Broadwell Y Base" },
+ { PCH_WPT_BDW_H, "Broadwell H" },
+};
+
+static struct {
+ u16 igdid;
+ const char *name;
+} igd_table[] = {
+ { IGD_HASWELL_ULT_GT1, "Haswell ULT GT1" },
+ { IGD_HASWELL_ULT_GT2, "Haswell ULT GT2" },
+ { IGD_HASWELL_ULT_GT3, "Haswell ULT GT3" },
+ { IGD_BROADWELL_U_GT1, "Broadwell U GT1" },
+ { IGD_BROADWELL_U_GT2, "Broadwell U GT2" },
+ { IGD_BROADWELL_U_GT3_15W, "Broadwell U GT3 (15W)" },
+ { IGD_BROADWELL_U_GT3_28W, "Broadwell U GT3 (28W)" },
+ { IGD_BROADWELL_Y_GT2, "Broadwell Y GT2" },
+ { IGD_BROADWELL_H_GT2, "Broadwell U GT2" },
+ { IGD_BROADWELL_H_GT3, "Broadwell U GT3" },
+};
+
+static void report_cpu_info(void)
+{
+ struct cpuid_result cpuidr;
+ u32 i, index;
+ char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
+ int vt, txt, aes;
+ msr_t microcode_ver;
+ const char *mode[] = {"NOT ", ""};
+ const char *cpu_type = "Unknown";
+
+ index = 0x80000000;
+ cpuidr = cpuid(index);
+ if (cpuidr.eax < 0x80000004) {
+ strcpy(cpu_string, "Platform info not available");
+ } else {
+ u32 *p = (u32*) cpu_string;
+ for (i = 2; i <= 4 ; i++) {
+ cpuidr = cpuid(index + i);
+ *p++ = cpuidr.eax;
+ *p++ = cpuidr.ebx;
+ *p++ = cpuidr.ecx;
+ *p++ = cpuidr.edx;
+ }
+ }
+ /* Skip leading spaces in CPU name string */
+ while (cpu_name[0] == ' ')
+ cpu_name++;
+
+ microcode_ver.lo = 0;
+ microcode_ver.hi = 0;
+ wrmsr(0x8B, microcode_ver);
+ cpuidr = cpuid(1);
+ microcode_ver = rdmsr(0x8b);
+
+ /* Look for string to match the name */
+ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
+ if (cpu_table[i].cpuid == cpuidr.eax) {
+ cpu_type = cpu_table[i].name;
+ break;
+ }
+ }
+
+ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
+ printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
+ cpuidr.eax, cpu_type, microcode_ver.hi);
+
+ aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
+ txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
+ vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+ printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, "
+ "VT %ssupported\n", mode[aes], mode[txt], mode[vt]);
+}
+
+static void report_mch_info(void)
+{
+ int i;
+ u16 mch_device = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID);
+ u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
+ const char *mch_type = "Unknown";
+
+ /* Look for string to match the revision for Broadwell U/Y */
+ if (mch_device == MCH_BROADWELL_ID_U_Y) {
+ for (i = 0; i < ARRAY_SIZE(mch_rev_table); i++) {
+ if (mch_rev_table[i].revid == mch_revision) {
+ mch_type = mch_rev_table[i].name;
+ break;
+ }
+ }
+ }
+
+ printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
+ mch_device, mch_revision, mch_type);
+}
+
+static void report_pch_info(void)
+{
+ int i;
+ u16 lpcid = pch_type();
+ const char *pch_type = "Unknown";
+
+ for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+ if (pch_table[i].lpcid == lpcid) {
+ pch_type = pch_table[i].name;
+ break;
+ }
+ }
+ printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
+ lpcid, pch_revision(), pch_type);
+}
+
+static void report_igd_info(void)
+{
+ int i;
+ u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);
+ const char *igd_type = "Unknown";
+
+ for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
+ if (igd_table[i].igdid == igdid) {
+ igd_type = igd_table[i].name;
+ break;
+ }
+ }
+ printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
+ igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type);
+}
+
+void report_platform_info(void)
+{
+ report_cpu_info();
+ report_mch_info();
+ report_pch_info();
+ report_igd_info();
+}
+
+/*
+ * Dump in the log memory controller configuration as read from the memory
+ * controller registers.
+ */
+void report_memory_config(void)
+{
+ u32 addr_decoder_common, addr_decode_ch[2];
+ int i;
+
+ addr_decoder_common = MCHBAR32(0x5000);
+ addr_decode_ch[0] = MCHBAR32(0x5004);
+ addr_decode_ch[1] = MCHBAR32(0x5008);
+
+ printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
+ (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
+ printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
+ addr_decoder_common & 3,
+ (addr_decoder_common >> 2) & 3,
+ (addr_decoder_common >> 4) & 3);
+
+ for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
+ u32 ch_conf = addr_decode_ch[i];
+ printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
+ i, ch_conf);
+ printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
+ ((ch_conf >> 22) & 1) ? "on" : "off");
+ printk(BIOS_DEBUG, " rank interleave %s\n",
+ ((ch_conf >> 21) & 1) ? "on" : "off");
+ printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n",
+ ((ch_conf >> 0) & 0xff) * 256,
+ ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
+ ((ch_conf >> 17) & 1) ? "dual" : "single",
+ ((ch_conf >> 16) & 1) ? "" : ", selected");
+ printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n",
+ ((ch_conf >> 8) & 0xff) * 256,
+ ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
+ ((ch_conf >> 18) & 1) ? "dual" : "single",
+ ((ch_conf >> 16) & 1) ? ", selected" : "");
+ }
+}
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
new file mode 100644
index 0000000000..c026004eaf
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -0,0 +1,164 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/cbfs.h>
+#include <arch/stages.h>
+#include <arch/early_variables.h>
+#include <console/console.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <cpu/x86/mtrr.h>
+#include <elog.h>
+#include <romstage_handoff.h>
+#include <stage_cache.h>
+#include <timestamp.h>
+#include <soc/me.h>
+#include <soc/pei_data.h>
+#include <soc/pm.h>
+#include <soc/reset.h>
+#include <soc/romstage.h>
+#include <soc/spi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Entry from cache-as-ram.inc. */
+void * asmlinkage romstage_main(unsigned long bist,
+ uint32_t tsc_low, uint32_t tsc_hi)
+{
+ struct romstage_params rp = {
+ .bist = bist,
+ .pei_data = NULL,
+ };
+
+ post_code(0x30);
+
+ /* Save initial timestamp from bootblock. */
+ timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
+
+ /* Save romstage begin */
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ /* System Agent Early Initialization */
+ systemagent_early_init();
+
+ /* PCH Early Initialization */
+ pch_early_init();
+
+ /* Call into mainboard pre console init. Needed to enable serial port
+ on IT8772 */
+ mainboard_pre_console_init();
+
+ /* Start console drivers */
+ console_init();
+
+ /* Get power state */
+ rp.power_state = fill_power_state();
+
+ /* Print useful platform information */
+ report_platform_info();
+
+ /* Set CPU frequency to maximum */
+ set_max_freq();
+
+ /* Call into mainboard. */
+ mainboard_romstage_entry(&rp);
+
+#if CONFIG_CHROMEOS
+ save_chromeos_gpios();
+#endif
+
+ return setup_stack_and_mttrs();
+}
+
+static inline void chromeos_init(int prev_sleep_state)
+{
+#if CONFIG_CHROMEOS
+ /* Normalize the sleep state to what init_chromeos() wants for S3: 2 */
+ init_chromeos(prev_sleep_state == SLEEP_STATE_S3 ? 2 : 0);
+#endif
+}
+
+/* Entry from the mainboard. */
+void romstage_common(struct romstage_params *params)
+{
+ struct romstage_handoff *handoff;
+
+ post_code(0x32);
+
+ timestamp_add_now(TS_BEFORE_INITRAM);
+
+ params->pei_data->boot_mode = params->power_state->prev_sleep_state;
+
+#if CONFIG_ELOG_BOOT_COUNT
+ if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
+ boot_count_increment();
+#endif
+
+ /* Print ME state before MRC */
+ intel_me_status();
+
+ /* Save ME HSIO version */
+ intel_me_hsio_version(&params->power_state->hsio_version,
+ &params->power_state->hsio_checksum);
+
+ /* Initialize RAM */
+ raminit(params->pei_data);
+
+ timestamp_add_now(TS_AFTER_INITRAM);
+
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = (params->power_state->prev_sleep_state ==
+ SLEEP_STATE_S3);
+ else
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
+
+ chromeos_init(params->power_state->prev_sleep_state);
+}
+
+void asmlinkage romstage_after_car(void)
+{
+ timestamp_add_now(TS_END_ROMSTAGE);
+
+ /* Load the ramstage. */
+ copy_and_run();
+ while (1);
+}
+
+void ramstage_cache_invalid(void)
+{
+#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
+ /* Perform cold reset on invalid ramstage cache. */
+ reset_system();
+#endif
+}
+
+#if CONFIG_CHROMEOS
+int vboot_get_sw_write_protect(void)
+{
+ u8 status;
+ /* Return unprotected status if status read fails. */
+ return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
+}
+
+#endif
+void __attribute__((weak)) mainboard_pre_console_init(void) {}
diff --git a/src/soc/intel/skylake/romstage/smbus.c b/src/soc/intel/skylake/romstage/smbus.c
new file mode 100644
index 0000000000..f09459bedd
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/smbus.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_def.h>
+#include <reg_script.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/smbus.h>
+#include <soc/romstage.h>
+
+static const struct reg_script smbus_init_script[] = {
+ /* Set SMBUS I/O base address */
+ REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1),
+ /* Set SMBUS enable */
+ REG_PCI_WRITE8(HOSTC, HST_EN),
+ /* Enable I/O access */
+ REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO),
+ /* Disable interrupts */
+ REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0),
+ /* Clear errors */
+ REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff),
+ /* Indicate the end of this array by REG_SCRIPT_END */
+ REG_SCRIPT_END,
+};
+
+void enable_smbus(void)
+{
+ reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
+}
+
+int smbus_read_byte(unsigned device, unsigned address)
+{
+ return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address);
+}
diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c
new file mode 100644
index 0000000000..a2c5d33a75
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/spi.c
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_def.h>
+#include <delay.h>
+#include <soc/spi.h>
+#include <soc/rcba.h>
+#include <soc/romstage.h>
+
+#define SPI_DELAY 10 /* 10us */
+#define SPI_RETRY 200000 /* 2s */
+
+static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
+{
+ u32 *ptr32 = (u32*)buffer;
+ u32 i;
+
+ /* Clear status bits */
+ SPIBAR16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR |
+ SPIBAR_HSFS_FDONE;
+
+ if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
+ printk(BIOS_ERR, "SPI ERROR: transaction in progress\n");
+ return -1;
+ }
+
+ /* Set flash address */
+ SPIBAR32(SPIBAR_FADDR) = offset;
+
+ /* Setup read transaction */
+ SPIBAR16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) |
+ SPIBAR_HSFC_CYCLE_READ;
+
+ /* Start transaction */
+ SPIBAR16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO;
+
+ /* Wait for completion */
+ for (i = 0; i < SPI_RETRY; i++) {
+ if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
+ /* Cycle in progress, wait 1ms */
+ udelay(SPI_DELAY);
+ continue;
+ }
+
+ if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) {
+ printk(BIOS_ERR, "SPI ERROR: Access Error\n");
+ return -1;
+
+ }
+
+ if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) {
+ printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n");
+ return -1;
+ }
+ break;
+ }
+
+ if (i >= SPI_RETRY) {
+ printk(BIOS_ERR, "SPI ERROR: Timeout\n");
+ return -1;
+ }
+
+ /* Read the data */
+ for (i = 0; i < size; i+=sizeof(u32)) {
+ if (size-i >= 4) {
+ /* reading >= dword */
+ *ptr32++ = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
+ } else {
+ /* reading < dword */
+ u8 j, *ptr8 = (u8*)ptr32;
+ u32 temp = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
+ for (j = 0; j < (size-i); j++) {
+ *ptr8++ = temp & 0xff;
+ temp >>= 8;
+ }
+ }
+ }
+
+ return size;
+}
+
+int early_spi_read(u32 offset, u32 size, u8 *buffer)
+{
+ u32 current = 0;
+
+ while (size > 0) {
+ u8 count = (size < 64) ? size : 64;
+ if (early_spi_read_block(offset + current, count,
+ buffer + current) < 0)
+ return -1;
+ size -= count;
+ current += count;
+ }
+
+ return 0;
+}
+
+/*
+ * Minimal set of commands to read WPSR from SPI.
+ * Don't use this code outside romstage -- it trashes the opmenu table.
+ * Returns 0 on success, < 0 on failure.
+ */
+int early_spi_read_wpsr(u8 *sr)
+{
+ int retry;
+
+ /* No address associated with rdsr */
+ SPIBAR8(SPIBAR_OPTYPE) = 0x0;
+ /* Setup opcode[0] = read wpsr */
+ SPIBAR8(SPIBAR_OPMENU_LOWER) = 0x5;
+
+ /* Start transaction */
+ SPIBAR16(SPIBAR_SSFC) = SPIBAR_SSFC_DATA | SPIBAR_SSFC_GO;
+
+ /* Wait for error / complete status */
+ for (retry = SPI_RETRY; retry; retry--) {
+ u16 status = SPIBAR16(SPIBAR_SSFS);
+ if (status & SPIBAR_SSFS_ERROR) {
+ printk(BIOS_ERR, "SPI rdsr failed\n");
+ return -1;
+ } else if (status & SPIBAR_SSFS_DONE) {
+ break;
+ }
+
+ udelay(SPI_DELAY);
+ }
+
+ *sr = SPIBAR32(SPIBAR_FDATA(0)) & 0xff;
+ return 0;
+}
diff --git a/src/soc/intel/skylake/romstage/stack.c b/src/soc/intel/skylake/romstage/stack.c
new file mode 100644
index 0000000000..a81eb07639
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/stack.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <arch/early_variables.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <cpu/x86/mtrr.h>
+#include <soc/romstage.h>
+
+static inline uint32_t *stack_push(u32 *stack, u32 value)
+{
+ stack = &stack[-1];
+ *stack = value;
+ return stack;
+}
+
+/* Romstage needs quite a bit of stack for decompressing images since the lzma
+ * lib keeps its state on the stack during romstage. */
+static unsigned long choose_top_of_stack(void)
+{
+ unsigned long stack_top;
+ const unsigned long romstage_ram_stack_size = 0x5000;
+
+ /* cbmem_add() does a find() before add(). */
+ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
+ romstage_ram_stack_size);
+ stack_top += romstage_ram_stack_size;
+ return stack_top;
+}
+
+/* setup_stack_and_mttrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
+void *setup_stack_and_mttrs(void)
+{
+ unsigned long top_of_stack;
+ int num_mtrrs;
+ uint32_t *slot;
+ uint32_t mtrr_mask_upper;
+ uint32_t top_of_ram;
+
+ /* Top of stack needs to be aligned to a 4-byte boundary. */
+ top_of_stack = choose_top_of_stack() & ~3;
+ slot = (void *)top_of_stack;
+ num_mtrrs = 0;
+
+ /* The upper bits of the MTRR mask need to set according to the number
+ * of physical address bits. */
+ mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
+
+ /* The order for each MTTR is value then base with upper 32-bits of
+ * each value coming before the lower 32-bits. The reasoning for
+ * this ordering is to create a stack layout like the following:
+ * +0: Number of MTRRs
+ * +4: MTTR base 0 31:0
+ * +8: MTTR base 0 63:32
+ * +12: MTTR mask 0 31:0
+ * +16: MTTR mask 0 63:32
+ * +20: MTTR base 1 31:0
+ * +24: MTTR base 1 63:32
+ * +28: MTTR mask 1 31:0
+ * +32: MTTR mask 1 63:32
+ */
+
+ /* Cache the ROM as WP just below 4GiB. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
+ num_mtrrs++;
+
+ /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ top_of_ram = (uint32_t)cbmem_top();
+ /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the
+ * start of the TSEG region. It is required to be 8MiB aligned. Set
+ * this area as cacheable so it can be used later for ramstage before
+ * setting up the entire RAM as cacheable. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /* Cache 8MiB at the top of ram. Top of ram is where the TSEG
+ * region resides. However, it is not restricted to SMM mode until
+ * SMM has been relocated. By setting the region to cacheable it
+ * provides faster access when relocating the SMM handler as well
+ * as using the TSEG region for other purposes. */
+ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
+ slot = stack_push(slot, 0); /* upper base */
+ slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /* Save the number of MTTRs to setup. Return the stack location
+ * pointing to the number of MTRRs. */
+ slot = stack_push(slot, num_mtrrs);
+
+ return slot;
+}
diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c
new file mode 100644
index 0000000000..7a43917601
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/systemagent.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <reg_script.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/systemagent.h>
+
+static const struct reg_script systemagent_early_init_script[] = {
+ REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1),
+ REG_PCI_WRITE32(DMIBAR, DMI_BASE_ADDRESS | 1),
+ REG_PCI_WRITE32(EPBAR, EP_BASE_ADDRESS | 1),
+ REG_MMIO_WRITE32(MCH_BASE_ADDRESS + EDRAMBAR, EDRAM_BASE_ADDRESS | 1),
+ REG_MMIO_WRITE32(MCH_BASE_ADDRESS + GDXCBAR, GDXC_BASE_ADDRESS | 1),
+
+ /* Set C0000-FFFFF to access RAM on both reads and writes */
+ REG_PCI_WRITE8(PAM0, 0x30),
+ REG_PCI_WRITE8(PAM1, 0x33),
+ REG_PCI_WRITE8(PAM2, 0x33),
+ REG_PCI_WRITE8(PAM3, 0x33),
+ REG_PCI_WRITE8(PAM4, 0x33),
+ REG_PCI_WRITE8(PAM5, 0x33),
+ REG_PCI_WRITE8(PAM6, 0x33),
+
+ /* Device enable: IGD and Mini-HD */
+ REG_PCI_WRITE32(DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN),
+
+ REG_SCRIPT_END
+};
+
+void systemagent_early_init(void)
+{
+ reg_script_run_on_dev(SA_DEV_ROOT, systemagent_early_init_script);
+}
diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c
new file mode 100644
index 0000000000..96c96343f1
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/uart.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/early_variables.h>
+#include <arch/io.h>
+#include <delay.h>
+#include <device/pci_def.h>
+#include <reg_script.h>
+#include <stdint.h>
+#include <uart8250.h>
+#include <soc/iobp.h>
+#include <soc/serialio.h>
+
+const struct reg_script uart_init[] = {
+ /* Set MMIO BAR */
+ REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE),
+ /* Enable Memory access and Bus Master */
+ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER),
+ /* Initialize LTR */
+ REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_GEN,
+ ~SIO_REG_PPR_GEN_LTR_MODE_MASK, 0),
+ REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
+ ~(SIO_REG_PPR_RST_ASSERT), 0),
+ /* Take UART out of reset */
+ REG_MMIO_OR32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
+ SIO_REG_PPR_RST_ASSERT),
+ /* Set M and N divisor inputs and enable clock */
+ REG_MMIO_WRITE32(CONFIG_TTYS0_BASE + SIO_REG_PPR_CLOCK,
+ SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
+ (SIO_REG_PPR_CLOCK_N_DIV << 16) |
+ (SIO_REG_PPR_CLOCK_M_DIV << 1)),
+ REG_SCRIPT_END
+};
+
+void pch_uart_init(void)
+{
+ /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
+ u32 gpiodf = 0x131f;
+ device_t dev;
+
+ /* Put UART in byte access mode for 16550 compatibility */
+ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {
+ case 0:
+ dev = PCH_DEV_UART0;
+ gpiodf |= SIO_IOBP_GPIODF_UART0_BYTE_ACCESS;
+ break;
+ case 1:
+ dev = PCH_DEV_UART1;
+ gpiodf |= SIO_IOBP_GPIODF_UART1_BYTE_ACCESS;
+ break;
+ default:
+ return;
+ }
+
+ /* Program IOBP GPIODF */
+ pch_iobp_update(SIO_IOBP_GPIODF, ~gpiodf, gpiodf);
+
+ /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
+ pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
+
+ /* Initialize chipset uart interface */
+ reg_script_run_on_dev(dev, uart_init);
+
+ /*
+ * Perform standard UART initialization
+ * Divisor 1 is 115200 BAUD
+ */
+ uart8250_mem_init(CONFIG_TTYS0_BASE, 1);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 05:01:58 +0000