summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake/smmrelocate.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/skylake/smmrelocate.c')
-rw-r--r--src/soc/intel/skylake/smmrelocate.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 4b6f1c4b60..8d2c545ae4 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -44,8 +44,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(SMRRphysBase_MSR, relo_params->smrr_base);
- wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask);
+ wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
@@ -191,7 +191,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
update_save_state(cpu, relo_params, runtime);
/* Write EMRR and SMRR MSRs based on indicated support. */
- mtrr_cap = rdmsr(MTRRcap_MSR);
+ mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (mtrr_cap.lo & SMRR_SUPPORTED)
write_smrr(relo_params);
}
@@ -230,7 +230,7 @@ static void fill_in_relocation_params(device_t dev,
/* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;
- params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid;
+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0;
/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
@@ -243,14 +243,14 @@ static void fill_in_relocation_params(device_t dev,
*/
params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
params->emrr_base.hi = 0;
- params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid;
+ params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
params->uncore_emrr_base.lo = emrr_base;
params->uncore_emrr_base.hi = 0;
params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
- MTRRphysMaskValid;
+ MTRR_PHYS_MASK_VALID;
params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
}