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Diffstat (limited to 'src/soc/intel/skylake/uart.c')
-rw-r--r--src/soc/intel/skylake/uart.c50
1 files changed, 48 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c
index 31389297b3..6f3c21e586 100644
--- a/src/soc/intel/skylake/uart.c
+++ b/src/soc/intel/skylake/uart.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2015-2017 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,11 +15,57 @@
*/
#include <cbmem.h>
+#include <console/uart.h>
#include <device/pci.h>
+#include <device/pci_def.h>
+#include <gpio.h>
+#include <intelblocks/lpss.h>
+#include <intelblocks/pcr.h>
#include <intelblocks/uart.h>
-#include <soc/iomap.h>
+#include <soc/bootblock.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+
+/* Serial IO UART controller legacy mode */
+#define PCR_SERIAL_IO_GPPRVRW7 0x618
+#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
+
+/* UART2 pad configuration. Support RXD and TXD for now. */
+static const struct pad_config uart2_pads[] = {
+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+};
+
+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
+uintptr_t uart_platform_base(int idx)
+{
+ /* Same base address for all debug port usage. In reality UART2
+ * is currently only supported. */
+ return UART_BASE_0_ADDR(idx);
+}
+#endif
+
+void pch_uart_init(void)
+{
+ uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+
+ uart_common_init(PCH_DEV_UART2, base);
+
+ /* Put UART2 in byte access mode for 16550 compatibility */
+ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
+ pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
+ PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
+
+ /*
+ * Dummy read after setting any of GPPRVRW7.
+ * Required for UART 16550 8-bit Legacy mode to become active
+ */
+ lpss_clk_read(base);
+ }
+
+ gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
#if !ENV_SMM
void pch_uart_read_resources(struct device *dev)