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-rw-r--r--src/soc/intel/skylake/Kconfig1
-rw-r--r--src/soc/intel/skylake/elog.c147
2 files changed, 11 insertions, 137 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 75d2d628d6..5116f3ab25 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -66,6 +66,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_UART
+ select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c
index 7a8932b50f..359f3e612a 100644
--- a/src/soc/intel/skylake/elog.c
+++ b/src/soc/intel/skylake/elog.c
@@ -22,6 +22,7 @@
#include <stdint.h>
#include <elog.h>
#include <intelblocks/pmclib.h>
+#include <intelblocks/xhci.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/smbus.h>
@@ -42,142 +43,13 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
#define XHCI_USB3_PORT_STATUS_REG 0x540
#define XHCI_USB2_PORT_NUM 10
#define XHCI_USB3_PORT_NUM 6
-/* Wake on disconnect enable */
-#define XHCI_STATUS_WDE (1 << 26)
-/* Wake on connect enable */
-#define XHCI_STATUS_WCE (1 << 25)
-/* Port link status change */
-#define XHCI_STATUS_PLC (1 << 22)
-/* Connect status change */
-#define XHCI_STATUS_CSC (1 << 17)
-/* Port link status */
-#define XHCI_STATUS_PLS_SHIFT (5)
-#define XHCI_STATUS_PLS_MASK (0xF << XHCI_STATUS_PLS_SHIFT)
-#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT)
-
-static bool pch_xhci_csc_set(uint32_t port_status)
-{
- return !!(port_status & XHCI_STATUS_CSC);
-}
-
-static bool pch_xhci_wake_capable(uint32_t port_status)
-{
- return !!((port_status & XHCI_STATUS_WCE) |
- (port_status & XHCI_STATUS_WDE));
-}
-
-static bool pch_xhci_plc_set(uint32_t port_status)
-{
- return !!(port_status & XHCI_STATUS_PLC);
-}
-
-static bool pch_xhci_resume(uint32_t port_status)
-{
- return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME;
-}
-
-/*
- * Check if a particular USB port caused wake by:
- * 1. Change in connect/disconnect status (if enabled)
- * 2. USB device activity
- *
- * Params:
- * base : MMIO address of first port.
- * num : Number of ports.
- * event : Event that needs to be added in case wake source is found.
- *
- * Return value:
- * true : Wake source was found.
- * false : Wake source was not found.
- */
-static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num,
- uint32_t event)
-{
- uint8_t i;
- uint32_t port_status;
- bool found = false;
-
- for (i = 0; i < num; i++, base += 0x10) {
- /* Read port status and control register for the port. */
- port_status = read32((void *)base);
-
- /* Ensure that the status is not all 1s. */
- if (port_status == 0xffffffff)
- continue;
-
- /*
- * Check if CSC bit is set and port is capable of wake on
- * connect/disconnect to identify if the port caused wake
- * event for usb attach/detach.
- */
- if (pch_xhci_csc_set(port_status) &&
- pch_xhci_wake_capable(port_status)) {
- elog_add_event_wake(event, i + 1);
- found = true;
- continue;
- }
-
- /*
- * Check if PLC is set and PLS indicates resume to identify if
- * the port caused wake event for usb activity.
- */
- if (pch_xhci_plc_set(port_status) &&
- pch_xhci_resume(port_status)) {
- elog_add_event_wake(event, i + 1);
- found = true;
- }
- }
- return found;
-}
-/*
- * Update elog event and instance depending upon the USB2 port that caused
- * the wake event.
- *
- * Return value:
- * true = Indicates that USB2 wake event was found.
- * false = Indicates that USB2 wake event was not found.
- */
-static inline bool pch_xhci_usb2_update_wake_event(uintptr_t mmio_base)
-{
- return pch_xhci_port_wake_check(mmio_base + XHCI_USB2_PORT_STATUS_REG,
- XHCI_USB2_PORT_NUM,
- ELOG_WAKE_SOURCE_PME_XHCI_USB_2);
-}
-
-/*
- * Update elog event and instance depending upon the USB3 port that caused
- * the wake event.
- *
- * Return value:
- * true = Indicates that USB3 wake event was found.
- * false = Indicates that USB3 wake event was not found.
- */
-static inline bool pch_xhci_usb3_update_wake_event(uintptr_t mmio_base)
-{
- return pch_xhci_port_wake_check(mmio_base + XHCI_USB3_PORT_STATUS_REG,
- XHCI_USB3_PORT_NUM,
- ELOG_WAKE_SOURCE_PME_XHCI_USB_3);
-}
-
-#ifdef __SIMPLE_DEVICE__
-static bool pch_xhci_update_wake_event(pci_devfn_t dev)
-#else
-static bool pch_xhci_update_wake_event(struct device *dev)
-#endif
-{
- uintptr_t mmio_base;
- bool event_found = false;
- mmio_base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16);
-
- if (pch_xhci_usb2_update_wake_event(mmio_base))
- event_found = true;
-
- if (pch_xhci_usb3_update_wake_event(mmio_base))
- event_found = true;
-
- return event_found;
-}
+static const struct xhci_usb_info usb_info = {
+ .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
+ .num_usb2_ports = XHCI_USB2_PORT_NUM,
+ .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
+ .num_usb3_ports = XHCI_USB3_PORT_NUM,
+};
struct pme_status_info {
#ifdef __SIMPLE_DEVICE__
@@ -203,7 +75,8 @@ static void pch_log_add_elog_event(const struct pme_status_info *info,
* If wake source is XHCI, check for detailed wake source events on
* USB2/3 ports.
*/
- if ((info->dev == PCH_DEV_XHCI) && pch_xhci_update_wake_event(dev))
+ if ((info->dev == PCH_DEV_XHCI) &&
+ pch_xhci_update_wake_event(&usb_info))
return;
elog_add_event_wake(info->elog_event, 0);
@@ -251,7 +124,7 @@ static void pch_log_pme_internal_wake_source(void)
* PME_STS_BIT in controller register.
*/
if (!dev_found)
- dev_found = pch_xhci_update_wake_event(PCH_DEV_XHCI);
+ dev_found = pch_xhci_update_wake_event(&usb_info);
if (!dev_found)
elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);