summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/Kconfig5
-rw-r--r--src/soc/intel/skylake/chip.c12
-rw-r--r--src/soc/intel/skylake/chip.h25
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c12
-rw-r--r--src/soc/intel/skylake/gspi.c16
-rw-r--r--src/soc/intel/skylake/i2c.c15
-rw-r--r--src/soc/intel/skylake/include/soc/soc_chip.h21
-rw-r--r--src/soc/intel/skylake/lockdown.c21
8 files changed, 69 insertions, 58 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index bfaa19f5d6..13b18dc151 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
@@ -329,6 +330,10 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 2
+config SOC_INTEL_I2C_DEV_MAX
+ int
+ default 6
+
config CPU_BCLK_MHZ
int
default 100
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 9fe19d8f9b..466db0950e 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -69,6 +69,14 @@ static void soc_enable(struct device *dev)
dev->ops = &cpu_bus_ops;
}
+static int get_lockdown_config(void)
+{
+ const struct soc_intel_common_config *soc_config;
+ soc_config = chip_get_common_soc_structure();
+
+ return soc_config->chipset_lockdown;
+}
+
struct chip_operations soc_intel_skylake_ops = {
CHIP_NAME("Intel Skylake")
.enable_dev = &soc_enable,
@@ -145,7 +153,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SataMode = config->SataMode;
params->LockDownConfigGlobalSmi = config->LockDownConfigGlobalSmi;
params->LockDownConfigRtcLock = config->LockDownConfigRtcLock;
- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
+ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
params->LockDownConfigBiosInterface = 0;
params->LockDownConfigBiosLock = 0;
params->LockDownConfigSpiEiss = 0;
@@ -173,7 +181,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SkipMpInit = !config->use_fsp_mp_init;
- for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
+ for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
/*
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 8b98662b1e..3c85ad5a3d 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -3,7 +3,7 @@
*
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,6 +22,7 @@
#include <arch/acpi_device.h>
#include <device/i2c_simple.h>
#include <drivers/i2c/designware/dw_i2c.h>
+#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
#include <stdint.h>
#include <soc/gpe.h>
@@ -33,14 +34,16 @@
#include <soc/usb.h>
#include <soc/vr_config.h>
-#define SKYLAKE_I2C_DEV_MAX 6
-
enum skylake_i2c_voltage {
I2C_VOLTAGE_3V3,
I2C_VOLTAGE_1V8
};
struct soc_intel_skylake_config {
+
+ /* Common struct containing soc config data required by common code */
+ struct soc_intel_common_config common_soc_config;
+
/*
* Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled.
@@ -273,11 +276,7 @@ struct soc_intel_skylake_config {
/* I2C */
/* Bus voltage level, default is 3.3V */
- enum skylake_i2c_voltage i2c_voltage[SKYLAKE_I2C_DEV_MAX];
- struct dw_i2c_bus_config i2c[SKYLAKE_I2C_DEV_MAX];
-
- /* GSPI */
- struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX];
/* Camera */
u8 Cio2Enable;
@@ -544,16 +543,6 @@ struct soc_intel_skylake_config {
* 0b - Disabled
*/
u8 eist_enable;
- /* Chipset (LPC and SPI) Lock Down
- * 1b - coreboot to handle lockdown
- * 0b - FSP to handle lockdown
- */
- enum {
- /* lock according to binary UPD settings */
- CHIPSET_LOCKDOWN_FSP,
- /* coreboot handles locking */
- CHIPSET_LOCKDOWN_COREBOOT,
- } chipset_lockdown;
/*
* Activates VR mailbox command for Intersil VR C-state issues.
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 227e244224..ebfad667bb 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -211,6 +211,14 @@ static void soc_enable(struct device *dev)
dev->ops = &cpu_bus_ops;
}
+static int get_lockdown_config(void)
+{
+ const struct soc_intel_common_config *soc_config;
+ soc_config = chip_get_common_soc_structure();
+
+ return soc_config->chipset_lockdown;
+}
+
struct chip_operations soc_intel_skylake_ops = {
CHIP_NAME("Intel 6th Gen")
.enable_dev = &soc_enable,
@@ -352,7 +360,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
* do the changes and then lock it back in coreboot during finalize.
*/
tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0;
- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
+ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
tconfig->PchLockDownBiosInterface = 0;
params->PchLockDownBiosLock = 0;
params->PchLockDownSpiEiss = 0;
@@ -389,7 +397,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CpuConfig.Bits.SkipMpInit = !config->use_fsp_mp_init;
- for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
+ for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c
index 252be7771c..ed36c7a15a 100644
--- a/src/soc/intel/skylake/gspi.c
+++ b/src/soc/intel/skylake/gspi.c
@@ -16,6 +16,7 @@
#include <assert.h>
#include <device/device.h>
+#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
#include <intelblocks/spi.h>
#include <soc/iomap.h>
@@ -23,19 +24,10 @@
const struct gspi_cfg *gspi_get_soc_cfg(void)
{
- DEVTREE_CONST struct soc_intel_skylake_config *config;
- int devfn = SA_DEVFN_ROOT;
- DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
+ const struct soc_intel_common_config *common_config;
+ common_config = chip_get_common_soc_structure();
- if (!dev || !dev->chip_info) {
- printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
- __func__);
- return NULL;
- }
-
- config = dev->chip_info;
-
- return &config->gspi[0];
+ return &common_config->gspi[0];
}
uintptr_t gspi_get_soc_early_base(void)
diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c
index baf6335ced..c9070fe5a0 100644
--- a/src/soc/intel/skylake/i2c.c
+++ b/src/soc/intel/skylake/i2c.c
@@ -15,6 +15,7 @@
#include <console/console.h>
#include <device/device.h>
+#include <intelblocks/chip.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
@@ -22,18 +23,10 @@
const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)
{
- const struct soc_intel_skylake_config *config;
- const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
+ const struct soc_intel_common_config *common_config;
+ common_config = chip_get_common_soc_structure();
- if (!dev || !dev->chip_info) {
- printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
- __func__);
- return NULL;
- }
-
- config = dev->chip_info;
-
- return &config->i2c[bus];
+ return &common_config->i2c[bus];
}
uintptr_t dw_i2c_get_soc_early_base(unsigned int bus)
diff --git a/src/soc/intel/skylake/include/soc/soc_chip.h b/src/soc/intel/skylake/include/soc/soc_chip.h
new file mode 100644
index 0000000000..f9e7e4fc64
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/soc_chip.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_SKYLAKE_SOC_CHIP_H_
+#define _SOC_SKYLAKE_SOC_CHIP_H_
+
+#include "../../chip.h"
+
+#endif /* _SOC_SKYLAKE_SOC_CHIP_H_ */
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index 600be27957..fd1f5b2206 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -16,6 +16,7 @@
#include <arch/io.h>
#include <bootstate.h>
#include <chip.h>
+#include <intelblocks/chip.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
@@ -27,7 +28,7 @@
#define PCR_DMI_GCS 0x274C
#define PCR_DMI_GCS_BILD (1 << 0)
-static void lpc_lockdown_config(const struct soc_intel_skylake_config *config)
+static void lpc_lockdown_config(const struct soc_intel_common_config *config)
{
/* Set Bios Interface Lock, Bios Lock */
if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
@@ -63,7 +64,8 @@ static void dmi_lockdown_config(void)
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
}
-static void spi_lockdown_config(const struct soc_intel_skylake_config *config)
+static void fast_spi_lockdown_config(const
+ struct soc_intel_common_config *config)
{
/* Set FAST_SPI opcode menu */
fast_spi_set_opcode_menu();
@@ -86,21 +88,14 @@ static void spi_lockdown_config(const struct soc_intel_skylake_config *config)
static void platform_lockdown_config(void *unused)
{
- struct soc_intel_skylake_config *config;
- struct device *dev;
-
- dev = PCH_DEV_SPI;
- /* Check if device is valid, else return */
- if (dev == NULL || dev->chip_info == NULL)
- return;
-
- config = dev->chip_info;
+ const struct soc_intel_common_config *common_config;
+ common_config = chip_get_common_soc_structure();
/* LPC lock down configuration */
- lpc_lockdown_config(config);
+ lpc_lockdown_config(common_config);
/* SPI lock down configuration */
- spi_lockdown_config(config);
+ fast_spi_lockdown_config(common_config);
/* DMI lock down configuration */
dmi_lockdown_config();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 12:18:07 +0000