diff options
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 25 | ||||
| -rw-r--r-- | src/soc/intel/skylake/finalize.c | 46 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/p2sb.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/p2sb.c | 46 |
6 files changed, 57 insertions, 66 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef95cf7767..89e48f1232 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -16,6 +16,7 @@ bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += gpio.c bootblock-y += gspi.c +bootblock-y += p2sb.c bootblock-y += pmutil.c bootblock-y += spi.c bootblock-y += lpc.c @@ -54,6 +55,7 @@ ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c ramstage-y += memmap.c +ramstage-y += p2sb.c ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c @@ -68,6 +70,7 @@ ramstage-y += vr_config.c smm-y += elog.c smm-y += gpio.c +smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-$(CONFIG_UART_DEBUG) += uart.c diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index cc8f43725b..2c3df09cc4 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -33,6 +33,7 @@ #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/p2sb.h> #include <intelblocks/sgx.h> #include <intelblocks/uart.h> #include <intelblocks/systemagent.h> diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index ef61a60291..4c88ed55bf 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -22,9 +22,10 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> -#include <intelblocks/rtc.h> #include <intelblocks/pmclib.h> +#include <intelblocks/rtc.h> #include <intelblocks/smbus.h> #include <soc/bootblock.h> #include <soc/iomap.h> @@ -44,29 +45,11 @@ #define PCR_DMI_PMBASEC 0x27B0 #define PCR_DMI_TCOBASE 0x2778 -static void enable_p2sbbar(void) -{ - pci_devfn_t dev = PCH_DEV_P2SB; - - /* Enable PCR Base address in PCH */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); - - /* Enable P2SB MSE */ - pci_write_config8(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - /* - * Enable decoding for HPET memory address range. - * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode - * the High Performance Timer memory address range - * selected by bits 1:0 - */ - pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); -} - void bootblock_pch_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); - enable_p2sbbar(); + p2sb_enable_bar(); + p2sb_configure_hpet(); } static void soc_config_acpibase(void) diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index e640ceb40a..12dbab4814 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -40,40 +40,9 @@ #define PCR_PSFX_T0_SHDW_PCIEN 0x1C #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) -static void pch_configure_endpoints(struct device *dev, int epmask_id, - uint32_t mask) +static void disable_sideband_access(void) { - uint32_t reg32; - - reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id)); - pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); -} - -static void disable_sideband_access(struct device *dev) -{ - u8 reg8; - uint32_t mask; - - /* - * Set p2sb PCI offset EPMASK5 C4h [29, 28, 27, 26] to disable Sideband - * access for PCI Root Bridge. - * Set p2sb PCI offset EPMASK5 C4h [17, 16,10, 1] to disable Sideband - * access for MIPI controller. - */ - mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | - (1 << 16) | (1 << 10) | (1 << 1); - pch_configure_endpoints(dev, 5, mask); - - /* - * Set p2sb PCI offset EPMASK7 CCh ports E6, E5 (bits 6, 5) - * to disable Sideband access for XHCI controller. - */ - mask = (1 << 6) | (1 << 5); - pch_configure_endpoints(dev, 7, mask); - - /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ - reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2); - pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1)); + p2sb_disable_sideband_access(); /* hide p2sb device */ p2sb_hide(); @@ -81,15 +50,6 @@ static void disable_sideband_access(struct device *dev) static void pch_disable_heci(void) { - struct device *dev = PCH_DEV_P2SB; - - /* - * if p2sb device 1f.1 is not present or hidden in devicetree - * p2sb device becomes NULL - */ - if (!dev) - return; - /* unhide p2sb device */ p2sb_unhide(); @@ -97,7 +57,7 @@ static void pch_disable_heci(void) pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); - disable_sideband_access(dev); + disable_sideband_access(); } static void pch_finalize_script(struct device *dev) diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h index 09e73fc254..8d7c11af75 100644 --- a/src/soc/intel/skylake/include/soc/p2sb.h +++ b/src/soc/intel/skylake/include/soc/p2sb.h @@ -23,9 +23,7 @@ #define PCH_P2SB_HBDF 0x70 #define PCH_P2SB_EPMASK0 0xB0 -#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) -#define PCH_P2SB_E0 0xE0 #define PCH_PWRM_ACPI_TMR_CTL 0xFC #endif /* _SOC_P2SB_H_ */ diff --git a/src/soc/intel/skylake/p2sb.c b/src/soc/intel/skylake/p2sb.c new file mode 100644 index 0000000000..c1e9118248 --- /dev/null +++ b/src/soc/intel/skylake/p2sb.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <intelblocks/p2sb.h> + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ + uint32_t mask; + + if (count != P2SB_EP_MASK_MAX_REG) { + printk(BIOS_ERR, "Unable to program EPMASK registers\n"); + return; + } + + /* + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband + * access for PCI Root Bridge. + * Set p2sb PCI offset EPMASK5 [17, 16,10, 1] to disable Sideband + * access for MIPI controller. + */ + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | + (1 << 16) | (1 << 10) | (1 << 1); + + ep_mask[P2SB_EP_MASK_5_REG] = mask; + + /* + * Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband + * access for XHCI controller. + */ + mask = (1 << 6) | (1 << 5); + + ep_mask[P2SB_EP_MASK_7_REG] = mask; +} |