diff options
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/fsp20/soc/romstage.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pm.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/reset.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/pmc.c | 30 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 133 |
8 files changed, 172 insertions, 19 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a4dee51b39..62e28e693c 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -359,6 +359,10 @@ struct soc_intel_skylake_config { * 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue */ u8 SendVrMbxCmd; + + /* Enable/Disable VMX feature */ + u8 VmxEnable; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254; diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index d48ac67ab3..08753f1ee9 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -21,10 +21,16 @@ #include <fsp/api.h> asmlinkage void *car_stage_c_entry(void); -void mainboard_memory_init_params(struct FSPM_UPD *mupd); - +void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index e0bf8b0c3a..235ad898e0 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -183,6 +183,9 @@ uint8_t *pmc_mmio_regs(void); /* Get base address of TCO I/O registers. */ uint16_t smbus_tco_regs(void); +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + static inline int deep_s3_enabled(void) { uint32_t deep_s3_pol; diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index ab251ce05f..638a151a9d 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -17,7 +17,7 @@ #include <fsp/util.h> #include <reset.h> -void chipset_handle_reset(enum fsp_status status) +void chipset_handle_reset(uint32_t status) { switch(status) { case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index e552c396d4..877712f58e 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,6 +1,7 @@ verstage-y += power_state.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage.S +romstage-y += pmc.c romstage-y += power_state.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c diff --git a/src/soc/intel/skylake/romstage/pmc.c b/src/soc/intel/skylake/romstage/pmc.c new file mode 100644 index 0000000000..e9d06f2c31 --- /dev/null +++ b/src/soc/intel/skylake/romstage/pmc.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/pci_devs.h> +#include <soc/pm.h> + +void pmc_set_disb(void) +{ + /* Set the DISB after DRAM init */ + u32 disb_val = 0; + pci_devfn_t dev = PCH_DEV_PMC; + disb_val = pci_read_config32(dev, GEN_PMCON_A); + disb_val |= DISB; + + /* Don't clear bits that are write-1-to-clear */ + disb_val &= ~(GBL_RST_STS | MS4V); + pci_write_config32(dev, GEN_PMCON_A, disb_val); +} diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 0ec2f99e63..97c6a4526e 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -243,11 +243,5 @@ void soc_after_ram_init(struct romstage_params *params) /* Set the DISB as soon as possible after DRAM * init and MRC cache is saved. */ - u32 disb_val = 0; - device_t dev = PCH_DEV_PMC; - disb_val = pci_read_config32(dev, GEN_PMCON_A); - disb_val |= DISB; - /* Preserve bits which get cleared up if written 1 */ - disb_val &= ~(GBL_RST_STS | MS4V); - pci_write_config32(dev, GEN_PMCON_A, disb_val); + pmc_set_disb(); } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8a15a69a23..8e083234a0 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -13,32 +13,147 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> +#include <arch/early_variables.h> +#include <arch/io.h> +#include <arch/symbols.h> +#include <assert.h> +#include <cpu/x86/mtrr.h> +#include <cbmem.h> +#include <chip.h> #include <console/console.h> +#include <device/pci_def.h> #include <fsp/util.h> +#include <fsp/memmap.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/romstage.h> +#include <timestamp.h> +#include <vboot/vboot_common.h> + +/* + * Romstage needs some stack for decompressing ramstage images, since the lzma + * lib keeps its state on the stack during romstage. + */ +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 asmlinkage void *car_stage_c_entry(void) { - bool s3wake = false; + bool s3wake; + struct postcar_frame pcf; + uintptr_t top_of_ram; + struct chipset_power_state *ps; + console_init(); - /* TODO: Add fill_powerstate and determine sleep state. */ + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + + ps = fill_power_state(); + timestamp_add_now(TS_START_ROMSTAGE); + s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); - return NULL; + pmc_set_disb(); + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, + MTRR_TYPE_WRBACK); + } + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1, + CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + return postcar_commit_mtrrs(&pcf); } -static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg) + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) { - /* TODO: Fill SoC specific Memory init Params */ -} + const struct device *dev; + const struct soc_intel_skylake_config *config; + int i; + uint32_t mask = 0; -void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){ + /* Set the parameters for MemoryInit */ + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + config = dev->chip_info; + /* + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not + * have access to the bios_reserved range so it always assumes 8MB is + * used and so the kernel will avoid the last 8MB of the stolen window. + * With the default stolen size of 32MB(-8MB) there is not enough space + * for FBC to work with a high resolution panel. + */ + m_cfg->IgdDvmt50PreAlloc = 2; + m_cfg->MmioSize = 0x800; /* 2GB in MB */ + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->ProbelessTrace = config->ProbelessTrace; + m_cfg->EnableTraceHub = config->EnableTraceHub; + if (vboot_recovery_mode_enabled()) + m_cfg->SaGv = 0; /* Disable SaGv in recovery mode. */ + else + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->Rmt; + m_cfg->DdrFreqLimit = config->DdrFreqLimit; + m_cfg->VmxEnable = config->VmxEnable; + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1<<i); + } + m_cfg->PcieRpEnableMask = mask; +} - struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; soc_memory_init_params(m_cfg); + + /* Enable DMI Virtual Channel for ME */ + m_t_cfg->DmiVcm = 0x01; + + /* Enable Sending DID to ME */ + m_t_cfg->SendDidMsg = 0x01; + m_t_cfg->DidInitStat = 0x01; + mainboard_memory_init_params(mupd); + + /* Reserve enough memory under TOLUD to save CBMEM header */ + mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); + } -__attribute__((weak)) void mainboard_memory_init_params(struct FSPM_UPD *mupd) +__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) { /* Do nothing */ } |