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-rw-r--r--src/soc/intel/skylake/Makefile.inc3
-rw-r--r--src/soc/intel/skylake/memmap.c106
2 files changed, 0 insertions, 109 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index cb0906c1d5..b049e84795 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -33,7 +33,6 @@ verstage-y += uart.c
romstage-y += gpio.c
romstage-y += gspi.c
romstage-y += i2c.c
-romstage-y += memmap.c
romstage-y += me.c
romstage-y += pmc.c
romstage-y += pmutil.c
@@ -54,7 +53,6 @@ ramstage-y += irq.c
ramstage-y += lockdown.c
ramstage-y += lpc.c
ramstage-y += me.c
-ramstage-y += memmap.c
ramstage-y += p2sb.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
@@ -76,7 +74,6 @@ smm-y += smihandler.c
smm-y += uart.c
smm-y += xhci.c
-postcar-y += memmap.c
postcar-y += gspi.c
postcar-y += spi.c
postcar-y += i2c.c
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
deleted file mode 100644
index 63e7acdb85..0000000000
--- a/src/soc/intel/skylake/memmap.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/romstage.h>
-#include <cbmem.h>
-#include <fsp/util.h>
-#include <intelblocks/ebda.h>
-#include <intelblocks/systemagent.h>
-#include <stdlib.h>
-
-/*
- * Fill up memory layout information
- *
- * Host Memory Map:
- *
- * +--------------------------+ TOUUD
- * | |
- * +--------------------------+ 4GiB
- * | PCI Address Space |
- * +--------------------------+ TOLUD (also maps into MC address space)
- * | iGD |
- * +--------------------------+ BDSM
- * | GTT |
- * +--------------------------+ BGSM
- * | TSEG |
- * +--------------------------+ TSEGMB
- * | DMA Protected Region |
- * +--------------------------+ DPR
- * | PRM (C6DRAM/SGX) |
- * +--------------------------+ PRMRR
- * | ME Stolen Memory |
- * +--------------------------+ ME Stolen
- * | PTT |
- * +--------------------------+ top_of_ram
- * | Reserved - FSP/CBMEM |
- * +--------------------------+ TOLUM
- * | Usage DRAM |
- * +--------------------------+ 0
- *
- * Some of the base registers above can be equal making the size of those
- * regions 0. The reason is because the memory controller internally subtracts
- * the base registers from each other to determine sizes of the regions. In
- * other words, the memory map is in a fixed order no matter what.
- */
-void fill_soc_memmap_ebda(struct ebda_config *cfg)
-{
- struct range_entry tolum;
-
- fsp_find_bootloader_tolum(&tolum);
- cfg->cbmem_top = range_entry_end(&tolum);
-}
-
-void cbmem_top_init(void)
-{
- /* Fill up EBDA area */
- fill_ebda_area();
-}
-
-/*
- * +-------------------------+ Top of RAM (aligned)
- * | System Management Mode |
- * | code and data | Length: CONFIG_TSEG_SIZE
- * | (TSEG) |
- * +-------------------------+ SMM base (aligned)
- * | |
- * | Chipset Reserved Memory |
- * | |
- * +-------------------------+ top_of_ram (aligned)
- * | |
- * | CBMEM Root |
- * | |
- * +-------------------------+
- * | |
- * | FSP Reserved Memory |
- * | |
- * +-------------------------+
- * | |
- * | Various CBMEM Entries |
- * | |
- * +-------------------------+ top_of_stack (8 byte aligned)
- * | |
- * | stack (CBMEM Entry) |
- * | |
- * +-------------------------+
- */
-void *cbmem_top_chipset(void)
-{
- struct ebda_config ebda_cfg;
-
- retrieve_ebda_object(&ebda_cfg);
-
- return (void *)(uintptr_t)ebda_cfg.cbmem_top;
-}