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-rw-r--r--src/soc/intel/skylake/memmap.c13
1 files changed, 2 insertions, 11 deletions
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 4c3c58a12d..29f2517468 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -296,8 +296,6 @@ void *cbmem_top(void)
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this
@@ -310,14 +308,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+ /* Cache the TSEG region */
+ postcar_enable_tseg_cache(pcf);
}
#endif