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-rw-r--r--src/soc/intel/tigerlake/Kconfig8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 7bb533ab71..be4e26c2cc 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -74,22 +74,22 @@ config DCACHE_RAM_BASE
default 0xfef00000
config DCACHE_RAM_SIZE
- default 0x40000
+ default 0x80000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.
config DCACHE_BSP_STACK_SIZE
hex
- default 0x20400
+ default 0x30400
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be
- sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
+ sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE
hex
- default 0x10000
+ default 0x20000
help
The amount of anticipated heap usage in CAR by FSP.
Refer to Platform FSP integration guide document to know