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Diffstat (limited to 'src/soc/intel/tigerlake/bootblock')
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c23
-rw-r--r--src/soc/intel/tigerlake/bootblock/report_platform.c5
2 files changed, 2 insertions, 26 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index b0646018c6..94b70721df 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -39,8 +39,7 @@
#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x1100
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0xA00
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100
#define PCR_PSFX_TO_SHDW_BAR0 0
#define PCR_PSFX_TO_SHDW_BAR1 0x4
#define PCR_PSFX_TO_SHDW_BAR2 0x8
@@ -60,20 +59,6 @@
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
-static uint32_t get_pmc_reg_base(void)
-{
- uint8_t pch_series;
-
- pch_series = get_pch_series();
-
- if (pch_series == PCH_TGP)
- return PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP;
- else if (pch_series == PCH_JSP)
- return PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP;
- else
- return 0;
-}
-
static void soc_config_pwrmbase(void)
{
uint32_t reg32;
@@ -116,11 +101,7 @@ void bootblock_pch_early_init(void)
static void soc_config_acpibase(void)
{
uint32_t pmc_reg_value;
- uint32_t pmc_base_reg;
-
- pmc_base_reg = get_pmc_reg_base();
- if (!pmc_base_reg)
- die_with_post_code(POST_HW_INIT_FAILURE, "Invalid PMC base address\n");
+ uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE;
pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c
index d7b2e0db32..59091c112f 100644
--- a/src/soc/intel/tigerlake/bootblock/report_platform.c
+++ b/src/soc/intel/tigerlake/bootblock/report_platform.c
@@ -37,7 +37,6 @@ static struct {
const char *name;
} cpu_table[] = {
{ CPUID_TIGERLAKE_A0, "Tigerlake A0" },
- { CPUID_JASPERLAKE_A0, "Jasperlake A0" },
};
static struct {
@@ -48,7 +47,6 @@ static struct {
{ PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" },
{ PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" },
{ PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" },
- { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake-1" },
{ PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" },
{ PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" },
};
@@ -89,7 +87,6 @@ static struct {
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" },
- { PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, "Jasperlake Super" },
{ PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" },
{ PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" },
{ PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" },
@@ -105,8 +102,6 @@ static struct {
{ PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" },
{ PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" },
{ PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" },
- { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" },
- { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" },
{ PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" },
{ PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" },
{ PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" },