diff options
Diffstat (limited to 'src/soc/intel/tigerlake/romstage/fsp_params_tgl.c')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 3872b61cf7..c5629a51c6 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -15,9 +15,11 @@ #include <assert.h> #include <console/console.h> +#include <cpu/x86/msr.h> #include <fsp/util.h> #include <soc/gpio_soc_defs.h> #include <soc/iomap.h> +#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> @@ -38,6 +40,16 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->RMT; + /* CpuRatio Settings */ + if (config->cpu_ratio_override) { + m_cfg->CpuRatio = config->cpu_ratio_override; + } else { + /* Set CpuRatio to match existing MSR value */ + msr_t flex_ratio; + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + } + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1 << i); |