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Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index cf24021841..885a6f9df3 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -109,7 +109,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
params->SkipMpInit = 0;
} else {
- params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
+ params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
}
/* D3Hot and D3Cold for TCSS */
@@ -277,8 +277,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE;
/* Legacy 8254 timer support */
- params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
- params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
+ params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
+ params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
/* Enable Hybrid storage auto detection */
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite()